Inventor · disambiguated record
Kenneth Alan Dockser
Also filed as: DOCKSER KENNETH · DOCKSER KENNETH A · DOCKSER KENNETH ALAN
38 granted patents·7 pending applications·903 citations·filing 1994–2020
98Inventor score
Top patents by PatentIndex Score
45 records- 0190US7624256B2System and method wherein conditional instructions unconditionally provide outputQUALCOMM INC·Filed 2005·Granted Nov 24, 2009·24 cites·15 claims
- 0289US5860119AData-packet fifo buffer system with end-of-packet flagsVLSI TECHNOLOGY INC·Filed 1996·Granted Jan 12, 1999·155 cites·1 claims
- 0388US7725519B2Floating-point processor with selectable subprecisionQUALCOMM INC·Filed 2005·Granted May 25, 2010·19 cites·31 claims
- 0485US9164772B2Hybrid queue for storing instructions from fetch queue directly in out-of-order queue or temporarily in in-order queue until space is availableDOCKSER KENNETH ALAN·Filed 2012·Granted Oct 20, 2015·10 cites·23 claims
- 0585US8447800B2Mode-based multiply-add recoding for denormal operandsDOCKSER KENNETH ALAN·Filed 2011·Granted May 21, 2013·11 cites·2 claims
- 0684US8595279B2Floating-point processor with reduced power requirements for selectable subprecisionDOCKSER KENNETH ALAN·Filed 2006·Granted Nov 26, 2013·14 cites·33 claims
- 0783US7836284B2Microprocessor with automatic selection of processing parallelism mode based on width data of instructionsQUALCOMM INC·Filed 2005·Granted Nov 16, 2010·13 cites·20 claims
- 0881US7912887B2Mode-based multiply-add recoding for denormal operandsQUALCOMM INC·Filed 2006·Granted Mar 22, 2011·12 cites·14 claims
- 0980US7694114B2Software selectable adjustment of SIMD parallelismQUALCOMM INC·Filed 2005·Granted Apr 6, 2010·8 cites·10 claims
- 1080US7386747B2Method and system for reducing power consumption of a programmable processorQUALCOMM INC·Filed 2005·Granted Jun 10, 2008·10 cites·20 claims
- 1180US5841684AMethod and apparatus for computer implemented constant multiplication with multipliers having repeated patterns including shifting of replicas and patterns having at least two digit positions with non-zero valuesVLSI TECHNOLOGY INC·Filed 1997·Granted Nov 24, 1998·91 cites·9 claims
- 1278US5586069AArithmetic logic unit with zero sum predictionVLSI TECHNOLOGY INC·Filed 1994·Granted Dec 17, 1996·67 cites·1 claims
- 1376US5481686AFloating-point processor with apparent-precision based selection of execution-precisionVLSI TECHNOLOGY INC·Filed 1995·Granted Jan 2, 1996·79 cites·7 claims
- 1475US5815422AComputer-implemented multiplication with shifting of pattern-product partialsVLSI TECHNOLOGY INC·Filed 1997·Granted Sep 29, 1998·73 cites·5 claims
- 1574US5963454AMethod and apparatus for efficiently implementing complex function blocks in integrated circuit designsVLSI TECHNOLOGY INC·Filed 1996·Granted Oct 5, 1999·68 cites·31 claims
- 1672US5706466AVon Neumann system with harvard processor and instruction bufferVLSI TECHNOLOGY INC·Filed 1995·Granted Jan 6, 1998·65 cites·12 claims
- 1771US9304774B2Processor with a coprocessor having early access to not-yet issued instructionsDOCKSER KENNETH ALAN·Filed 2012·Granted Apr 5, 2016·3 cites·24 claims
- 1871US8122231B2Software selectable adjustment of SIMD parallelismDOCKSER KENNETH ALAN·Filed 2010·Granted Feb 21, 2012·2 cites·20 claims
- 1969US8566568B2Method and apparatus for executing processor instructions based on a dynamically alterable delayMICHALAK GERALD PAUL·Filed 2006·Granted Oct 22, 2013·5 cites·1 claims
- 2064US7725625B2Latency insensitive FIFO signaling protocolQUALCOMM INC·Filed 2008·Granted May 25, 2010·2 cites·20 claims
- 2162US9146706B2Controlled-precision iterative arithmetic logic unitDOCKSER KENNETH ALAN·Filed 2006·Granted Sep 29, 2015·2 cites·27 claims
- 2258US8082287B2Pre-saturating fixed-point multiplierDOCKSER KENNETH ALAN·Filed 2006·Granted Dec 20, 2011·1 cites·15 claims
- 2355US6006030AMicroprocessor with programmable instruction trap for deimplementing instructionsVLSI TECHNOLOGY INC·Filed 1997·Granted Dec 21, 1999·29 cites·8 claims
- 2453US8799627B2Software selectable adjustment of SIMD parallelismDOCKSER KENNETH ALAN·Filed 2012·Granted Aug 5, 2014·0 cites·15 claims
- 2552US6029243AFloating-point processor with operand-format precision greater than execution precisionVLSI TECHNOLOGY INC·Filed 1997·Granted Feb 22, 2000·27 cites·8 claims
- 2651US5764357AZero-run-length encoder with shift registerVLSI TECHNOLOGY INC·Filed 1996·Granted Jun 9, 1998·15 cites·4 claims
- 2750US5649174AMicroprocessor with instruction-cycle versus clock-frequency mode selectionVLSI TECHNOLOGY INC·Filed 1994·Granted Jul 15, 1997·21 cites·10 claims
- 2850US5613151AData processor with flexible register mapping schemeFiled 1995·Granted Mar 18, 1997·24 cites·4 claims
- 2949US9823929B2Optimizing performance for context-dependent instructionsQUALCOMM INC·Filed 2013·Granted Nov 21, 2017·0 cites·32 claims
- 3048US7454538B2Latency insensitive FIFO signaling protocolQUALCOMM INC·Filed 2005·Granted Nov 18, 2008·0 cites·14 claims
- 3147US9471325B2Method and apparatus for selective renaming in a microprocessorQUALCOMM INC·Filed 2013·Granted Oct 18, 2016·0 cites·30 claims
- 3247US5862370AData processor system with instruction substitution filter for deimplementing instructionsVLSI TECHNOLOGY INC·Filed 1995·Granted Jan 19, 1999·20 cites·10 claims
- 3346US5604689AArithmetic logic unit with zero-result predictionVLSI TECHNOLOGY INC·Filed 1996·Granted Feb 18, 1997·15 cites·5 claims
- 3445US9514061B1Method and apparatus for cache tag compressionQUALCOMM INC·Filed 2015·Granted Dec 6, 2016·0 cites·25 claims
- 3543US9753694B2Division and root computation with fast result formattingQUALCOMM INC·Filed 2015·Granted Sep 5, 2017·0 cites·14 claims
- 3643US7793072B2Vector execution unit to process a vector instruction by executing a first operation on a first set of operands and a second operation on a second set of operandsIBM·Filed 2003·Granted Sep 7, 2010·1 cites·20 claims
- 3743US5603045AMicroprocessor system having instruction cache with reserved branch target sectionVLSI TECHNOLOGY INC·Filed 1994·Granted Feb 11, 1997·14 cites·3 claims
- 3843US2021091928A1Iterative cipher key-schedule cache for caching round keys used in an iterative encryption/decryption system and related methodsQUALCOMM INC·Filed 2020·Application pending·0 cites
- 3941US8200945B2Vector unit in a processor enabled to replicate data on a first portion of a data bus to primary and secondary registersCHATTERJEE SIDDHARTHA·Filed 2003·Granted Jun 12, 2012·3 cites·14 claims
- 4041US2013173886A1Processor with Hazard Tracking Employing Register Range ComparesDOCKSER KENNETH ALAN·Filed 2012·Application pending·0 cites
- 4141US2013218938A1Floating-point adder with operand shifting based on a predicted exponent differenceQUALCOMM INC·Filed 2013·Application pending·0 cites
- 4241US2012204008A1Processor with a Hybrid Instruction Queue with Instruction Elaboration Between SectionsDOCKSER KENNETH ALAN·Filed 2012·Application pending·0 cites
- 4340US2012110037A1Methods and Apparatus for a Read, Merge and Write Register FileDOCKSER KENNETH ALAN·Filed 2010·Application pending·0 cites
- 4439US2017255569A1Write-allocation for a cache based on execute permissionsQUALCOMM INC·Filed 2016·Application pending·0 cites
- 4534US2016313976A1High performance division and root computation unitQUALCOMM INC·Filed 2015·Application pending·0 cites
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