Assignee
DOCKSER KENNETH ALAN
US·8 granted patents·3 pending applications·43 citations·filing 2006–2012
Top patents by PatentIndex Score
11 records- 0185US9164772B2Hybrid queue for storing instructions from fetch queue directly in out-of-order queue or temporarily in in-order queue until space is availableDOCKSER KENNETH ALAN·Filed 2012·Granted Oct 20, 2015·10 cites·23 claims
- 0285US8447800B2Mode-based multiply-add recoding for denormal operandsDOCKSER KENNETH ALAN·Filed 2011·Granted May 21, 2013·11 cites·2 claims
- 0384US8595279B2Floating-point processor with reduced power requirements for selectable subprecisionDOCKSER KENNETH ALAN·Filed 2006·Granted Nov 26, 2013·14 cites·33 claims
- 0471US9304774B2Processor with a coprocessor having early access to not-yet issued instructionsDOCKSER KENNETH ALAN·Filed 2012·Granted Apr 5, 2016·3 cites·24 claims
- 0571US8122231B2Software selectable adjustment of SIMD parallelismDOCKSER KENNETH ALAN·Filed 2010·Granted Feb 21, 2012·2 cites·20 claims
- 0662US9146706B2Controlled-precision iterative arithmetic logic unitDOCKSER KENNETH ALAN·Filed 2006·Granted Sep 29, 2015·2 cites·27 claims
- 0758US8082287B2Pre-saturating fixed-point multiplierDOCKSER KENNETH ALAN·Filed 2006·Granted Dec 20, 2011·1 cites·15 claims
- 0853US8799627B2Software selectable adjustment of SIMD parallelismDOCKSER KENNETH ALAN·Filed 2012·Granted Aug 5, 2014·0 cites·15 claims
- 0941US2013173886A1Processor with Hazard Tracking Employing Register Range ComparesDOCKSER KENNETH ALAN·Filed 2012·Application pending·0 cites
- 1041US2012204008A1Processor with a Hybrid Instruction Queue with Instruction Elaboration Between SectionsDOCKSER KENNETH ALAN·Filed 2012·Application pending·0 cites
- 1140US2012110037A1Methods and Apparatus for a Read, Merge and Write Register FileDOCKSER KENNETH ALAN·Filed 2010·Application pending·0 cites
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