Inventor · disambiguated record
Mariano Layson Ching, Jr.
Also filed as: CHING JR MARIANO LAYSON · CHING MARIANO LAYSON
8 granted patents·1 pending application·11 citations·filing 2013–2024
77Inventor score
Technology areasH10W
Top patents by PatentIndex Score
9 records- 0183US10151658B2Pressure-sensing integrated circuit device with diaphragmNXP USA INC·Filed 2016·Granted Dec 11, 2018·6 cites·16 claims
- 0277US10446476B2Packaged integrated circuit having stacked die and method for thereforNXP USA INC·Filed 2018·Granted Oct 15, 2019·3 cites·17 claims
- 0361US2025219009A1Hybrid ball/bump and wirebond semiconductor device packagingNXP USA INC·Filed 2024·Application pending·0 cites
- 0459US9190353B2Lead frame and substrate semiconductor packageCHING JR MARIANO LAYSON·Filed 2013·Granted Nov 17, 2015·2 cites·9 claims
- 0556US11984408B2Cavity formed in a molding compound of a semiconductor package to reduce mechanical stress on a portion of a die in the package, and methods of formationNXP USA INC·Filed 2021·Granted May 14, 2024·0 cites·19 claims
- 0653US11923275B2Lead-frame assembly, semiconductor package and methods for improved adhesionNXP USA INC·Filed 2021·Granted Mar 5, 2024·0 cites·21 claims
- 0747US10847449B2Lead frame with selective patterned platingNXP USA INC·Filed 2019·Granted Nov 24, 2020·0 cites·19 claims
- 0846US10734311B2Hybrid lead frame for semiconductor die package with improved creepage distanceNXP USA INC·Filed 2019·Granted Aug 4, 2020·0 cites·20 claims
- 0939US10734327B2Lead reduction for improved creepage distanceNXP USA INC·Filed 2019·Granted Aug 4, 2020·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →