Inventor · disambiguated record
Taeg Ki Lim
Also filed as: LIM TAEG-KI
11 granted patents·2 pending applications·67 citations·filing 2005–2012
87Inventor score
Top patents by PatentIndex Score
13 records- 0193US7737539B2Integrated circuit package system including honeycomb moldingSTATS CHIPPAC LTD·Filed 2006·Granted Jun 15, 2010·30 cites·19 claims
- 0283US7656017B2Integrated circuit package system with thermo-mechanical interlocking substratesSTATS CHIPPAC LTD·Filed 2007·Granted Feb 2, 2010·14 cites·20 claims
- 0380US7443037B2Stacked integrated circuit package system with connection protectionSTATS CHIPPAC LTD·Filed 2006·Granted Oct 28, 2008·10 cites·20 claims
- 0471US8067831B2Integrated circuit package system with planar interconnectsKWON HYEOG CHAN·Filed 2005·Granted Nov 29, 2011·6 cites·20 claims
- 0561US8659175B2Integrated circuit package system with offset stackJU JONG WOOK·Filed 2007·Granted Feb 25, 2014·4 cites·19 claims
- 0661US8409921B2Integrated circuit package system including honeycomb moldingKUAN HEAP HOE·Filed 2010·Granted Apr 2, 2013·1 cites·20 claims
- 0759US8217501B2Integrated circuit package system including honeycomb moldingKWON HYEOG CHAN·Filed 2010·Granted Jul 10, 2012·1 cites·20 claims
- 0856US8618653B2Integrated circuit package system with wafer scale heat slugKO WONJUN·Filed 2008·Granted Dec 31, 2013·1 cites·20 claims
- 0947US8987056B2Integrated circuit package system with support carrier and method of manufacture thereofHA JONG-WOO·Filed 2008·Granted Mar 24, 2015·0 cites·19 claims
- 1047US7969023B2Integrated circuit package system with triple film spacer having embedded fillers and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2008·Granted Jun 28, 2011·0 cites·20 claims
- 1145US2013183777A1Method of forming phosphor layer on light-emitting device chip wafer using wafer level moldSAMSUNG ELECTRONICS CO LTD·Filed 2012·Application pending·0 cites
- 1244US8067275B2Integrated circuit package system with package integrationKO WONJUN·Filed 2007·Granted Nov 29, 2011·0 cites·20 claims
- 1342US2009191029A1System for handling semiconductor diesLIM TAEG KI·Filed 2008·Application pending·0 cites
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