Inventor · disambiguated record
Susan M. Eickhoff
Also filed as: EICKHOFF SUSAN M
18 granted patents·1 pending application·79 citations·filing 2011–2021
90Inventor score
Top patents by PatentIndex Score
19 records- 0195US8898504B2Parallel data communications mechanism having reduced power continuously calibrated linesBAUMGARTNER STEVEN J·Filed 2011·Granted Nov 25, 2014·57 cites·20 claims
- 0291US11379123B2Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory systemIBM·Filed 2021·Granted Jul 5, 2022·2 cites·17 claims
- 0390US10489069B2Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory systemIBM·Filed 2017·Granted Nov 26, 2019·5 cites·25 claims
- 0487US10395698B2Address/command chip controlled data chip address sequencing for a distributed memory buffer systemIBM·Filed 2017·Granted Aug 27, 2019·4 cites·14 claims
- 0586US10698440B2Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interfaceIBM·Filed 2018·Granted Jun 30, 2020·6 cites·20 claims
- 0686US10078461B1Partial data replay in a distributed memory buffer systemIBM·Filed 2017·Granted Sep 18, 2018·4 cites·1 claims
- 0764US11099601B2Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interfaceIBM·Filed 2019·Granted Aug 24, 2021·1 cites·20 claims
- 0864US10976939B2Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory systemIBM·Filed 2019·Granted Apr 13, 2021·0 cites·20 claims
- 0960US11687254B2Host synchronized autonomous data chip address sequencer for a distributed buffer memory systemIBM·Filed 2019·Granted Jun 27, 2023·0 cites·16 claims
- 1057US10353606B2Partial data replay in a distributed memory buffer systemIBM·Filed 2017·Granted Jul 16, 2019·0 cites·15 claims
- 1155US10534555B2Host synchronized autonomous data chip address sequencer for a distributed buffer memory systemIBM·Filed 2017·Granted Jan 14, 2020·0 cites·20 claims
- 1253US10162773B1Double data rate (DDR) memory read latency reductionIBM·Filed 2017·Granted Dec 25, 2018·0 cites·20 claims
- 1352US10740031B2Interface scheduler for a distributed memory systemIBM·Filed 2018·Granted Aug 11, 2020·0 cites·17 claims
- 1451US11587600B2Address/command chip controlled data chip address sequencing for a distributed memory buffer systemIBM·Filed 2019·Granted Feb 21, 2023·0 cites·20 claims
- 1551US2013188656A1Communicating Control Information for a Data Communications Link Via a Line Being CalibratedIBM·Filed 2013·Application pending·0 cites
- 1644US10771068B2Reducing chip latency at a clock boundary by reference clock phase adjustmentIBM·Filed 2018·Granted Sep 8, 2020·0 cites·14 claims
- 1743US10747442B2Host controlled data chip address sequencing for a distributed memory buffer systemIBM·Filed 2017·Granted Aug 18, 2020·0 cites·20 claims
- 1843US10642535B2Register access in a distributed memory buffer systemIBM·Filed 2018·Granted May 5, 2020·0 cites·20 claims
- 1936US10393805B2JTAG support over a broadcast bus in a distributed memory buffer systemIBM·Filed 2017·Granted Aug 27, 2019·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →