Inventor · disambiguated record
Silvia M. Mueller
Also filed as: MUELLER SILVIA · MUELLER SILVIA M · MUELLER SILVIA MELITTA
139 granted patents·24 pending applications·323 citations·filing 2003–2023
99Inventor score
Top patents by PatentIndex Score
163 records- 0196US11360769B1Decimal scale and convert and split to hexadecimal floating point instructionIBM·Filed 2021·Granted Jun 14, 2022·5 cites·20 claims
- 0294US10656913B2Enhanced low precision binary floating-point formattingIBM·Filed 2018·Granted May 19, 2020·9 cites·22 claims
- 0392US7694112B2Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computationIBM·Filed 2008·Granted Apr 6, 2010·37 cites·2 claims
- 0491US10235135B2Normalization of a product on a datapathIBM·Filed 2017·Granted Mar 19, 2019·6 cites·14 claims
- 0591US9684514B2Inference based condition code generationIBM·Filed 2014·Granted Jun 20, 2017·11 cites·2 claims
- 0691US8219605B2Decimal floating-pointing quantum exception detectionCOWLISHAW MICHAEL F·Filed 2010·Granted Jul 10, 2012·16 cites·23 claims
- 0790US9785435B1Floating point instruction with selectable comparison attributesIBM·Filed 2016·Granted Oct 10, 2017·7 cites·20 claims
- 0890US7461117B2Floating point unit with fused multiply add and method for calculating a result with a floating point unitIBM·Filed 2005·Granted Dec 2, 2008·30 cites·1 claims
- 0989US10592208B2Very low precision floating point representation for deep learning accelerationIBM·Filed 2018·Granted Mar 17, 2020·6 cites·19 claims
- 1086US8229989B2Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point unitsDHONG SANG HOO·Filed 2008·Granted Jul 24, 2012·14 cites·4 claims
- 1183US11132198B2Instruction handling for accumulation of register results in a microprocessorIBM·Filed 2019·Granted Sep 28, 2021·2 cites·25 claims
- 1283US10296294B2Multiply-add operations of binary numbers in an arithmetic unitIBM·Filed 2018·Granted May 21, 2019·3 cites·1 claims
- 1382US10430185B2Decimal load immediate instructionIBM·Filed 2017·Granted Oct 1, 2019·2 cites·11 claims
- 1481US11663004B2Vector convert hexadecimal floating point to scaled decimal instructionIBM·Filed 2021·Granted May 30, 2023·1 cites·25 claims
- 1581US10235170B2Decimal load immediate instructionIBM·Filed 2016·Granted Mar 19, 2019·2 cites·20 claims
- 1680US10346134B2Perform sign operation decimal instructionIBM·Filed 2017·Granted Jul 9, 2019·2 cites·11 claims
- 1780US10235137B2Decimal shift and divide instructionIBM·Filed 2017·Granted Mar 19, 2019·2 cites·8 claims
- 1880US8554822B2Decimal adder with end around carryCARLOUGH STEVEN R·Filed 2010·Granted Oct 8, 2013·6 cites·18 claims
- 1979US8291003B2Supporting multiple formats in a floating point processorBOERSMA MAARTEN J·Filed 2008·Granted Oct 16, 2012·11 cites·3 claims
- 2078US11099853B2Digit validation check control in instruction executionIBM·Filed 2019·Granted Aug 24, 2021·2 cites·20 claims
- 2178US11023205B2Negative zero control in instruction executionIBM·Filed 2019·Granted Jun 1, 2021·2 cites·20 claims
- 2278US8914431B2Range check based lookup tablesCARLOUGH STEVEN R·Filed 2012·Granted Dec 16, 2014·4 cites·15 claims
- 2377US10963219B2Hybrid floating point representation for deep learning accelerationIBM·Filed 2019·Granted Mar 30, 2021·2 cites·20 claims
- 2477US8578196B2Zero indication forwarding for floating point unit power reductionBAROWSKI HARRY S·Filed 2012·Granted Nov 5, 2013·3 cites·14 claims
- 2576US8949575B2Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latencyBOERSMA MAARTEN J·Filed 2011·Granted Feb 3, 2015·4 cites·10 claims
- 2675US10365892B2Decimal floating point instructions to perform directly on compressed decimal floating point dataIBM·Filed 2017·Granted Jul 30, 2019·2 cites·20 claims
- 2774US10379860B2Inference based condition code generationIBM·Filed 2017·Granted Aug 13, 2019·1 cites·4 claims
- 2874US10303438B2Fused-multiply-add floating-point operations on 128 bit wide operandsIBM·Filed 2017·Granted May 28, 2019·2 cites·23 claims
- 2974US9684515B2Inference based condition code generationIBM·Filed 2014·Granted Jun 20, 2017·2 cites·4 claims
- 3074US9122517B2Fused multiply-adder with booth-encodingBOERSMA MAARTEN J·Filed 2012·Granted Sep 1, 2015·3 cites·8 claims
- 3174US7058830B2Power saving in a floating point unit using a multiplier and aligner bypassIBM·Filed 2003·Granted Jun 6, 2006·21 cites·20 claims
- 3274US2023367597A1Instruction handling for accumulation of register results in a microprocessorIBM·Filed 2023·Application pending·0 cites
- 3373US10915385B2Residue prediction of packed dataIBM·Filed 2017·Granted Feb 9, 2021·1 cites·13 claims
- 3473US9430190B2Fused multiply add pipelineIBM·Filed 2014·Granted Aug 30, 2016·3 cites·20 claims
- 3572US11275561B2Mixed precision floating-point multiply-add operationIBM·Filed 2019·Granted Mar 15, 2022·1 cites·25 claims
- 3671US11755325B2Instruction handling for accumulation of register results in a microprocessorIBM·Filed 2021·Granted Sep 12, 2023·0 cites·19 claims
- 3771US10372417B2Multiply-add operations of binary numbers in an arithmetic unitIBM·Filed 2017·Granted Aug 6, 2019·1 cites·13 claims
- 3871US10175946B2Perform sign operation decimal instructionIBM·Filed 2016·Granted Jan 8, 2019·1 cites·20 claims
- 3971US10127015B2Decimal multiply and shift instructionIBM·Filed 2016·Granted Nov 13, 2018·1 cites·20 claims
- 4071US8346828B2System and method for storing numbers in first and second formats in a register fileIBM·Filed 2008·Granted Jan 1, 2013·5 cites·20 claims
- 4171US7137021B2Power saving in FPU with gated power based on opcodes and dataIBM·Filed 2003·Granted Nov 14, 2006·19 cites·12 claims
- 4270US10489115B2Shift amount correction for multiply-addIBM·Filed 2014·Granted Nov 26, 2019·2 cites·2 claims
- 4370US9348796B2Arithmetic operation in a data processing systemIBM·Filed 2013·Granted May 24, 2016·2 cites·10 claims
- 4470US8954485B2Range check based lookup tablesCARLOUGH STEVEN R·Filed 2012·Granted Feb 10, 2015·2 cites·10 claims
- 4569US9959093B2Binary fused multiply-add floating-point calculationsIBM·Filed 2016·Granted May 1, 2018·1 cites·14 claims
- 4669US9658828B2Decimal and binary floating point roundingIBM·Filed 2015·Granted May 23, 2017·1 cites·12 claims
- 4769US8407275B2Fast floating point compare with slower backup for corner casesBOERSMA MAARTEN J·Filed 2008·Granted Mar 26, 2013·4 cites·20 claims
- 4868US11755320B2Compute array of a processor with mixed-precision numerical linear algebra supportIBM·Filed 2021·Granted Sep 12, 2023·0 cites·20 claims
- 4968US11620105B2Hybrid floating point representation for deep learning accelerationIBM·Filed 2020·Granted Apr 4, 2023·0 cites·18 claims
- 5067US7290023B2High performance implementation of exponent adjustment in a floating point designIBM·Filed 2003·Granted Oct 30, 2007·13 cites·13 claims
Showing the top 50 of 163 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →