Inventor · disambiguated record
Abhijeet Ashok Chachad
Also filed as: CHACHAD ABHIJEET · CHACHAD ABHIJEET A · CHACHAD ABHIJEET ASHOK
109 granted patents·23 pending applications·347 citations·filing 2004–2025
99Inventor score
Files withTEXAS INSTRUMENTS INC109CHACHAD ABHIJEET ASHOK10DAMODARAN RAGURAM7TRAN JONATHAN SON HUNG3ANDERSON TIMOTHY DAVID1
Top patents by PatentIndex Score
132 records- 0198US11194617B2Merging data for write allocateTEXAS INSTRUMENTS INC·Filed 2020·Granted Dec 7, 2021·6 cites·18 claims
- 0298US10162641B2Highly integrated scalable, flexible DSP megamodule architectureTEXAS INSTRUMENTS INC·Filed 2017·Granted Dec 25, 2018·17 cites·16 claims
- 0398US9904645B2Multicore bus architecture with non-blocking high performance transaction credit systemTEXAS INSTRUMENTS INC·Filed 2014·Granted Feb 27, 2018·65 cites·40 claims
- 0498US9606803B2Highly integrated scalable, flexible DSP megamodule architectureTEXAS INSTRUMENTS INC·Filed 2014·Granted Mar 28, 2017·101 cites·54 claims
- 0597US12019514B2Handling non-correctable errorsTEXAS INSTRUMENTS INC·Filed 2022·Granted Jun 25, 2024·3 cites·20 claims
- 0697US11487616B2Write control for read-modify-write operations in cache memoryTEXAS INSTRUMENTS INC·Filed 2020·Granted Nov 1, 2022·5 cites·18 claims
- 0797US11416334B2Handling non-correctable errorsTEXAS INSTRUMENTS INC·Filed 2020·Granted Aug 16, 2022·5 cites·20 claims
- 0897US11237905B2Pipelined read-modify-write operations in cache memoryTEXAS INSTRUMENTS INC·Filed 2020·Granted Feb 1, 2022·5 cites·22 claims
- 0997US11036648B2Highly integrated scalable, flexible DSP megamodule architectureTEXAS INSTRUMENTS INC·Filed 2018·Granted Jun 15, 2021·6 cites·21 claims
- 1096US11816032B2Cache size changeTEXAS INSTRUMENTS INC·Filed 2022·Granted Nov 14, 2023·2 cites·20 claims
- 1196US11294707B2Global coherence operationsTEXAS INSTRUMENTS INC·Filed 2020·Granted Apr 5, 2022·4 cites·20 claims
- 1296US11249842B2Error correcting codes for multi-master memory controllerTEXAS INSTRUMENTS INC·Filed 2020·Granted Feb 15, 2022·4 cites·20 claims
- 1395US11768733B2Error correcting codes for multi-master memory controllerTEXAS INSTRUMENTS INC·Filed 2022·Granted Sep 26, 2023·2 cites·20 claims
- 1495US11609818B2Pipelined read-modify-write operations in cache memoryTEXAS INSTRUMENTS INC·Filed 2022·Granted Mar 21, 2023·2 cites·17 claims
- 1594US12505015B2Pipelined read-modify-write operations in cache memoryTEXAS INSTRUMENTS INC·Filed 2023·Granted Dec 23, 2025·1 cites·20 claims
- 1694US9298643B2Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirtyTEXAS INSTRUMENTS INC·Filed 2015·Granted Mar 29, 2016·7 cites·4 claims
- 1793US11307987B2Tag update bus for updated coherence stateTEXAS INSTRUMENTS INC·Filed 2020·Granted Apr 19, 2022·3 cites·20 claims
- 1893US8732416B2Requester based transaction status reporting in a system with multi-level memoryDAMODARAN RAGURAM·Filed 2011·Granted May 20, 2014·7 cites·13 claims
- 1992US2024411703A1Processor architecture with memory access circuitTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 2091US12056051B2Tag update bus for updated coherence stateTEXAS INSTRUMENTS INC·Filed 2022·Granted Aug 6, 2024·1 cites·20 claims
- 2191US2025013569A1Cache coherence shared state suppressionTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 2290US11138117B2Memory pipeline control in a hierarchical memory systemTEXAS INSTRUMENTS INC·Filed 2020·Granted Oct 5, 2021·2 cites·20 claims
- 2390US9244837B2Zero cycle clock invalidate operationTEXAS INSTRUMENTS INC·Filed 2012·Granted Jan 26, 2016·12 cites·5 claims
- 2490US2025328420A1Handling non-correctable errorsTEXAS INSTRUMENTS INC·Filed 2025·Application pending·0 cites
- 2589US12493522B2Write control for read-modify-write operations in cache memoryTEXAS INSTRUMENTS INC·Filed 2024·Granted Dec 9, 2025·0 cites·20 claims
- 2689US10713180B2Lookahead priority collection to support priority elevationTEXAS INSTRUMENTS INC·Filed 2018·Granted Jul 14, 2020·2 cites·16 claims
- 2789US10599433B2Cache management operations using streaming engineTEXAS INSTRUMENTS INC·Filed 2018·Granted Mar 24, 2020·4 cites·20 claims
- 2889US9268708B2Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherenceTEXAS INSTRUMENTS INC·Filed 2015·Granted Feb 23, 2016·3 cites·2 claims
- 2989US2025036522A1Parallelized scrubbing transactionsTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 3089US2025028551A1Global coherence operationsTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 3188US11307858B2Cache preload operations using streaming engineTEXAS INSTRUMENTS INC·Filed 2020·Granted Apr 19, 2022·2 cites·20 claims
- 3288US11119776B2Cache management operations using streaming engineTEXAS INSTRUMENTS INC·Filed 2020·Granted Sep 14, 2021·2 cites·20 claims
- 3388US10606596B2Cache preload operations using streaming engineTEXAS INSTRUMENTS INC·Filed 2018·Granted Mar 31, 2020·4 cites·20 claims
- 3488US9009408B2Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache systemCHACHAD ABHIJEET ASHOK·Filed 2011·Granted Apr 14, 2015·5 cites·4 claims
- 3588US8904260B2Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory schemeTRAN JONATHAN SON HUNG·Filed 2011·Granted Dec 2, 2014·7 cites·7 claims
- 3688US2024281278A1Pipeline arbitrationTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 3788US2024345956A1Tag update bus for updated coherence stateTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 3888US2024345868A1Pseudo-random way selectionTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 3987US12461775B2Controller with caching and non-caching modesTEXAS INSTRUMENTS INC·Filed 2024·Granted Nov 4, 2025·0 cites·20 claims
- 4087US12373286B2Handling non-correctable errorsTEXAS INSTRUMENTS INC·Filed 2024·Granted Jul 29, 2025·0 cites·20 claims
- 4187US12271314B2Cache size changeTEXAS INSTRUMENTS INC·Filed 2023·Granted Apr 8, 2025·0 cites·20 claims
- 4287US12197331B2Hardware coherence signaling protocolTEXAS INSTRUMENTS INC·Filed 2023·Granted Jan 14, 2025·0 cites·20 claims
- 4387US8904115B2Cache with multiple access pipelinesCHACHAD ABHIJEET ASHOK·Filed 2011·Granted Dec 2, 2014·4 cites·2 claims
- 4487US2025265193A1Hardware coherence for memory controllerTEXAS INSTRUMENTS INC·Filed 2025·Application pending·0 cites
- 4586US12321270B2Hardware coherence for memory controllerTEXAS INSTRUMENTS INC·Filed 2023·Granted Jun 3, 2025·0 cites·20 claims
- 4686US12135646B2Cache coherence shared state suppressionTEXAS INSTRUMENTS INC·Filed 2023·Granted Nov 5, 2024·0 cites·20 claims
- 4786US2025103502A1Memory pipeline control in a hierarchical memory systemTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 4885US12197332B2Memory pipeline control in a hierarchical memory systemTEXAS INSTRUMENTS INC·Filed 2024·Granted Jan 14, 2025·0 cites·20 claims
- 4985US12141601B2Global coherence operationsTEXAS INSTRUMENTS INC·Filed 2023·Granted Nov 12, 2024·0 cites·19 claims
- 5085US11106583B2Shadow caches for level 2 cache controllerTEXAS INSTRUMENTS INC·Filed 2020·Granted Aug 31, 2021·1 cites·20 claims
Showing the top 50 of 132 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →