Inventor · disambiguated record
Alexander Shubat
Also filed as: SHUBAT ALEXANDER
15 granted patents·395 citations·filing 1988–2008
94Inventor score
Top patents by PatentIndex Score
15 records- 0190US5402014APeripheral port with volatile and non-volatile configurationWAFERSCALE INTEGRATION INC·Filed 1993·Granted Mar 28, 1995·60 cites·10 claims
- 0289US4961172ADecoder for a memory address busWAFERSCALE INTEGRATION INC·Filed 1988·Granted Oct 2, 1990·61 cites·15 claims
- 0387US6392957B1Fast read/write cycle memory device having a self-timed read/write control circuitVIRAGE LOGIC CORP·Filed 2000·Granted May 21, 2002·47 cites·24 claims
- 0486US7002827B1Methods and apparatuses for a ROM memory array having a virtually grounded lineVIRAGE LOGIC CORP·Filed 2003·Granted Feb 21, 2006·45 cites·18 claims
- 0583US7692964B1Source-biased SRAM cell with reduced memory cell leakageVIRAGE LOGIC CORP·Filed 2006·Granted Apr 6, 2010·13 cites·15 claims
- 0680US7061794B1Wordline-based source-biasing scheme for reducing memory cell leakageVIRAGE LOGIC CORP·Filed 2004·Granted Jun 13, 2006·25 cites·30 claims
- 0780US6992938B1Methods and apparatuses for test circuitry for a dual-polarity non-volatile memory cellVIRAGE LOGIC CORP·Filed 2002·Granted Jan 31, 2006·28 cites·18 claims
- 0875US8112730B2Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilersALEKSANYAN KAREN·Filed 2008·Granted Feb 7, 2012·12 cites·17 claims
- 0973US6519202B1Method and apparatus to change the amount of redundant memory column and fuses associated with a memory deviceVIRAGE LOGIC CORP·Filed 2001·Granted Feb 11, 2003·20 cites·28 claims
- 1067US5453636AMOS SRAM cell with open base bipolar loadsWAFERSCALE INTEGRATION INC·Filed 1994·Granted Sep 26, 1995·27 cites·25 claims
- 1155US6269036B1System and method for testing multiple port memory devicesVIRAGE LOGIC CORP·Filed 1999·Granted Jul 31, 2001·15 cites·19 claims
- 1251US6051031AModule-based logic architecture and design flow for VLSI implementationVIRAGE LOGIC CORP·Filed 1997·Granted Apr 18, 2000·31 cites·74 claims
- 1349US6646933B1Method and apparatus to reduce the amount of redundant memory column and fuses associated with a memory deviceVIRAGE LOGIC CORP·Filed 2002·Granted Nov 11, 2003·6 cites·16 claims
- 1440US7904766B1Statistical yield of a system-on-a-chipSYNOPSYS INC·Filed 2007·Granted Mar 8, 2011·0 cites·20 claims
- 1537US4939392AOutput circuit for driving a memory device output lead including a three-state inverting buffer and a transfer gate coupled between the buffer input lead and the buffer output leadWAFERSCALE INTEGRATION INC·Filed 1988·Granted Jul 3, 1990·5 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →