Inventor · disambiguated record
Laurent Souef
Also filed as: SOUEF LAURENT
9 granted patents·3 pending applications·71 citations·filing 1996–2008
86Inventor score
Top patents by PatentIndex Score
12 records- 0161US6671870B2Computer implemented circuit synthesis systemKONINKL PHILIPS ELECTRONICS NV·Filed 2001·Granted Dec 30, 2003·9 cites·32 claims
- 0257US6311318B1Design for test area optimization algorithmVLSI TECHNOLOGY INC·Filed 1999·Granted Oct 30, 2001·18 cites·32 claims
- 0350US7870452B2Scan testing methodsNXP BV·Filed 2006·Granted Jan 11, 2011·3 cites·12 claims
- 0447US6970815B1Method of discriminating between different types of scan failures, computer readable code to cause a display to graphically depict one or more simulated scan output data sets versus time and a computer implemented circuit simulation and fault detection systemKONINKL PHILIPS ELECTRONICS NV·Filed 1999·Granted Nov 29, 2005·22 cites·24 claims
- 0542US7688103B2Cell with fixed output voltage for integrated circuitNXP BV·Filed 2008·Granted Mar 30, 2010·0 cites·9 claims
- 0638US5783874AKeypad handling circuitsVLSI TECHNOLOGY INC·Filed 1996·Granted Jul 21, 1998·8 cites·12 claims
- 0735US2010182033A1Testable integrated circuit and test methodNXP BV·Filed 2008·Application pending·0 cites
- 0834US7459928B2Cell with fixed output voltage for integrated circuitNXP BV·Filed 2003·Granted Dec 2, 2008·0 cites·14 claims
- 0934US5960052ALow power scannable counterVLSI TECHNOLOGY INC·Filed 1998·Granted Sep 28, 1999·6 cites·18 claims
- 1032US6141782APseudo-scan testing using hardware-accessible IC structuresVLSI TECHNOLOGY INC·Filed 1998·Granted Oct 31, 2000·5 cites·2 claims
- 1132US2002145458A1Clock-skew resistant chain of sequential cellsFiled 2002·Application pending·0 cites
- 1225US2003128022A1Method of testing an integrated circuit by simulationFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →