Inventor · disambiguated record
Munir D. Naeem
Also filed as: NAEEM MUNIR · NAEEM MUNIR D
23 granted patents·3 pending applications·361 citations·filing 1996–2013
95Inventor score
Top patents by PatentIndex Score
26 records- 0193US6284666B1Method of reducing RIE lag for deep trench silicon etchingIBM·Filed 2000·Granted Sep 4, 2001·87 cites·13 claims
- 0293US6002136AMicroscope specimen holder and grid arrangement for in-situ and ex-situ repeated analysisIBM·Filed 1998·Granted Dec 14, 1999·86 cites·21 claims
- 0386US6544838B2Method of deep trench formation with improved profile control and surface areaINFINEON TECHNOLOGIES AG·Filed 2001·Granted Apr 8, 2003·36 cites·30 claims
- 0478US8227311B2Method of forming enhanced capacitance trench capacitorCHENG KANGGUO·Filed 2010·Granted Jul 24, 2012·4 cites·15 claims
- 0574US5976986ALow pressure and low power C12 /HC1 process for sub-micron metal etchingIBM·Filed 1996·Granted Nov 2, 1999·50 cites·13 claims
- 0672US7358172B2Poly filled substrate contact on SOI structureIBM·Filed 2006·Granted Apr 15, 2008·4 cites·18 claims
- 0772US6821900B2Method for dry etching deep trenches in a substrateINFINEON TECHNOLOGIES AG·Filed 2001·Granted Nov 23, 2004·15 cites·30 claims
- 0869US8492821B2Enhanced capacitance trench capacitorCHENG KANGGUO·Filed 2012·Granted Jul 23, 2013·2 cites·12 claims
- 0969US7393738B1Subground rule STI fill for hot structureIBM·Filed 2007·Granted Jul 1, 2008·4 cites·18 claims
- 1068US7871893B2Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devicesIBM·Filed 2008·Granted Jan 18, 2011·4 cites·13 claims
- 1167US5846884AMethods for metal etching with reduced sidewall build up during integrated circuit manufacturingSIEMENS AG·Filed 1997·Granted Dec 8, 1998·34 cites·21 claims
- 1262US6893938B2STI formation for vertical and planar transistorsIBM·Filed 2003·Granted May 17, 2005·9 cites·48 claims
- 1361US8426268B2Embedded DRAM memory cell with additional patterning layer for improved strap formationCHENG KANGGUO·Filed 2010·Granted Apr 23, 2013·1 cites·8 claims
- 1461US8003488B2Shallow trench isolation structure compatible with SOI embedded DRAMIBM·Filed 2007·Granted Aug 23, 2011·2 cites·4 claims
- 1556US6555204B1Method of preventing bridging between polycrystalline micro-scale featuresIBM·Filed 2000·Granted Apr 29, 2003·6 cites·38 claims
- 1654US6551942B2Methods for etching tungsten stack structuresIBM·Filed 2001·Granted Apr 22, 2003·4 cites·17 claims
- 1752US6890815B2Reduced cap layer erosion for borderless contactsIBM·Filed 2003·Granted May 10, 2005·5 cites·25 claims
- 1851US7592245B2Poly filled substrate contact on SOI structureIBM·Filed 2008·Granted Sep 22, 2009·0 cites·9 claims
- 1951US6566219B2Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench openingINFINEON TECHNOLOGIES AG·Filed 2001·Granted May 20, 2003·4 cites·25 claims
- 2050US8772850B2Embedded DRAM memory cell with additional patterning layer for improved strap formationIBM·Filed 2013·Granted Jul 8, 2014·0 cites·14 claims
- 2150US6464806B1Method of forming extruded structures from polycrystalline materials and devices formed therebyIBM·Filed 2000·Granted Oct 15, 2002·3 cites·16 claims
- 2247US2008224255A1Subground rule sti fill for hot structureIBM·Filed 2008·Application pending·0 cites
- 2346US2009047791A1Semiconductor etching methodsIBM·Filed 2007·Application pending·0 cites
- 2446US2009104776A1Methods for forming nested and isolated lines in semiconductor devicesIBM·Filed 2007·Application pending·0 cites
- 2540US6733602B2Polycrystalline material with surface features projecting from a surface thereofIBM·Filed 2002·Granted May 11, 2004·0 cites·9 claims
- 2635US6359325B1Method of forming nano-scale structures from polycrystalline materials and nano-scale structures formed therebyIBM·Filed 2000·Granted Mar 19, 2002·1 cites·44 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →