Inventor · disambiguated record
Phillip F. Chapman
Also filed as: CHAPMAN PHILLIP F · CHAPMAN PHILLIP FRANCIS
18 granted patents·2 pending applications·70 citations·filing 1998–2018
93Inventor score
Top patents by PatentIndex Score
20 records- 0192US10170476B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2017·Granted Jan 1, 2019·5 cites·19 claims
- 0291US7498622B1Latchup robust gate array using through wafer viaIBM·Filed 2007·Granted Mar 3, 2009·23 cites·14 claims
- 0387US9842838B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2016·Granted Dec 12, 2017·3 cites·19 claims
- 0485US8017471B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2008·Granted Sep 13, 2011·7 cites·19 claims
- 0583US9397010B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2016·Granted Jul 19, 2016·2 cites·18 claims
- 0683US7549135B2Design methodology of guard ring design resistance optimization for latchup preventionIBM·Filed 2006·Granted Jun 16, 2009·13 cites·2 claims
- 0775US8987067B2Segmented guard ring structures with electrically insulated gap structures and design structures thereofIBM·Filed 2013·Granted Mar 24, 2015·3 cites·10 claims
- 0872US9275997B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2014·Granted Mar 1, 2016·1 cites·20 claims
- 0972US8021941B2Bias-controlled deep trench substrate noise isolation integrated circuit device structuresIBM·Filed 2009·Granted Sep 20, 2011·4 cites·3 claims
- 1070US8853789B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2013·Granted Oct 7, 2014·1 cites·6 claims
- 1169US8212332B2Bias-controlled deep trench substrate noise isolation integrated circuit device structuresCHAPMAN PHILLIP FRANCIS·Filed 2011·Granted Jul 3, 2012·3 cites·17 claims
- 1265US10978452B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryIBM·Filed 2018·Granted Apr 13, 2021·0 cites·18 claims
- 1365US8420518B2Structure and method of latchup robustness with placement of through wafer via within CMOS circuitryCHAPMAN PHILLIP F·Filed 2011·Granted Apr 16, 2013·1 cites·13 claims
- 1458US7855420B2Structure for a latchup robust array I/O using through wafer viaIBM·Filed 2008·Granted Dec 21, 2010·1 cites·11 claims
- 1557US7696541B2Structure for a latchup robust gate array using through wafer viaIBM·Filed 2008·Granted Apr 13, 2010·1 cites·9 claims
- 1652US2015035112A1Segmented guard ring structures with electrically insulated gap structures and design structures thereofIBM·Filed 2014·Application pending·0 cites
- 1747US2009166798A1Design methodology for guard ring design resistance optimization for latchup preventionIBM·Filed 2007·Application pending·0 cites
- 1843US7741681B2Latchup robust array I/O using through wafer viaIBM·Filed 2007·Granted Jun 22, 2010·0 cites·18 claims
- 1940US6391661B2Semiconductor and method of fabricatingIBM·Filed 2001·Granted May 21, 2002·1 cites·15 claims
- 2029US6229155B1Semiconductor and method of fabricatingIBM·Filed 1998·Granted May 8, 2001·1 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →