Inventor · disambiguated record
Kameswara K. Rao
Also filed as: RAO KAMESWARA K
38 granted patents·1 pending application·1,725 citations·filing 1983–2009
98Inventor score
Top patents by PatentIndex Score
39 records- 0197US7098689B1Disabling unused/inactive resources in programmable logic devices for static power reductionXILINX INC·Filed 2003·Granted Aug 29, 2006·79 cites·9 claims
- 0295US7581124B1Method and mechanism for controlling power consumption of an integrated circuitXILINX INC·Filed 2006·Granted Aug 25, 2009·50 cites·18 claims
- 0395US6366117B1Nonvolatile/battery-backed key in PLDXILINX INC·Filed 2000·Granted Apr 2, 2002·126 cites·7 claims
- 0495US6208549B1One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOSXILINX INC·Filed 2000·Granted Mar 27, 2001·98 cites·19 claims
- 0594US6931543B1Programmable logic device with decryption algorithm and decryption keyXILINX INC·Filed 2000·Granted Aug 16, 2005·114 cites·27 claims
- 0690US6044012ANon-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS processXILINX INC·Filed 1999·Granted Mar 28, 2000·81 cites·13 claims
- 0790US5200922ARedundancy circuit for high speed EPROM and flash memory devicesRAO KAMESWARA K·Filed 1990·Granted Apr 6, 1993·100 cites·4 claims
- 0890US4642798ACMOS E2 PROM decoding circuitINTEL CORP·Filed 1985·Granted Feb 10, 1987·65 cites·9 claims
- 0989US7562332B1Disabling unused/inactive resources in programmable logic devices for static power reductionXILINX INC·Filed 2006·Granted Jul 14, 2009·13 cites·20 claims
- 1089US7117373B1Bitstream for configuring a PLD with encrypted design dataXILINX INC·Filed 2000·Granted Oct 3, 2006·65 cites·20 claims
- 1187US4578777AOne step write circuit arrangement for EEPROMSSIGNETICS CORP·Filed 1983·Granted Mar 25, 1986·45 cites·28 claims
- 1286US7504854B1Regulating unused/inactive resources in programmable logic devices for static power reductionXILINX INC·Filed 2004·Granted Mar 17, 2009·29 cites·18 claims
- 1384US5689516AReset circuit for a programmable logic deviceXILINX INC·Filed 1996·Granted Nov 18, 1997·54 cites·10 claims
- 1483US8161355B2Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic processFUNG STEPHEN·Filed 2009·Granted Apr 17, 2012·18 cites·24 claims
- 1582US5949712ANon-volatile memory array using gate breakdown structureXILINX INC·Filed 1997·Granted Sep 7, 1999·48 cites·10 claims
- 1681US6549458B1Non-volatile memory array using gate breakdown structuresXILINX INC·Filed 2001·Granted Apr 15, 2003·25 cites·23 claims
- 1781US5949987AEfficient in-system programming structure and method for non-volatile programmable logic devicesXILINX INC·Filed 1998·Granted Sep 7, 1999·81 cites·5 claims
- 1881US5835402ANon-volatile storage for standard CMOS integrated circuitsXILINX INC·Filed 1997·Granted Nov 10, 1998·47 cites·9 claims
- 1981US5764076ACircuit for partially reprogramming an operational programmable logic deviceXILINX INC·Filed 1996·Granted Jun 9, 1998·40 cites·9 claims
- 2080US5914514ATwo transistor flash EPROM cellXILINX INC·Filed 1996·Granted Jun 22, 1999·47 cites·5 claims
- 2179US6055205ADecoder for a non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS processXILINX INC·Filed 1999·Granted Apr 25, 2000·42 cites·8 claims
- 2279US5661685AProgrammable logic device with configurable power supplyXILINX INC·Filed 1995·Granted Aug 26, 1997·95 cites·16 claims
- 2378US6265266B1Method of forming a two transistor flash EPROM cellXILINX INC·Filed 1996·Granted Jul 24, 2001·44 cites·31 claims
- 2478US6243294B1Memory architecture for non-volatile storage using gate breakdown structure in standard sub 0.35 micron processXILINX INC·Filed 2000·Granted Jun 5, 2001·25 cites·23 claims
- 2577US8099691B1Disabling unused/inactive resources in an integrated circuit for static power reductionTUAN TIM·Filed 2009·Granted Jan 17, 2012·6 cites·20 claims
- 2677US5523971ANon-volatile memory cell for programmable logic deviceXILINX INC·Filed 1995·Granted Jun 4, 1996·40 cites·11 claims
- 2776US6522582B1Non-volatile memory array using gate breakdown structuresXILINX INC·Filed 2000·Granted Feb 18, 2003·20 cites·39 claims
- 2876US6177830B1High voltage charge pump using standard sub 0.35 micron CMOS processXILINX INC·Filed 1999·Granted Jan 23, 2001·38 cites·8 claims
- 2975US7549139B1Tuning programmable logic devices for low-power design implementationXILINX INC·Filed 2004·Granted Jun 16, 2009·18 cites·19 claims
- 3069US7046071B1Series capacitor coupling multiplexer for programmable logic devicesXILINX INC·Filed 2003·Granted May 16, 2006·13 cites·20 claims
- 3166US6438065B1Redundancy architecture and method for non-volatile storageXILINX INC·Filed 2000·Granted Aug 20, 2002·14 cites·31 claims
- 3265US5838901AOverridable data protection mechanism for PLDsXILINX INC·Filed 1996·Granted Nov 17, 1998·40 cites·7 claims
- 3365US5734868AEfficient in-system programming structure and method for non-volatile programmable logic devicesFiled 1995·Granted Mar 31, 1998·40 cites·10 claims
- 3461US5959885ANon-volatile memory array using single poly EEPROM in standard CMOS processXILINX INC·Filed 1997·Granted Sep 28, 1999·20 cites·5 claims
- 3560US4903237ADifferential sense amplifier circuit for high speed ROMS, and flash memory devicesCATALYST SEMICONDUCTOR INC·Filed 1988·Granted Feb 20, 1990·17 cites·6 claims
- 3655US5991880AOverridable data protection mechanism for PLDsXILINX INC·Filed 1998·Granted Nov 23, 1999·25 cites·9 claims
- 3744US2010140680A1Double Polysilicon Process for Non-Volatile MemoryMOSYS INC·Filed 2008·Application pending·0 cites
- 3837US4566080AByte wide EEPROM with individual write circuitsSIGNETICS CORP·Filed 1983·Granted Jan 21, 1986·3 cites·5 claims
- 3930US8081521B2Two bits per cell non-volatile memory architectureCHUA CHEE T·Filed 2009·Granted Dec 20, 2011·0 cites·14 claims
Join the waitlist — get patent alerts
Get an alert when Kameswara K. Rao files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →