Inventor · disambiguated record
Nandor G. Thoma
Also filed as: THOMA NANDOR G · THOMA NANDOR GYORGY
24 granted patents·1 pending application·487 citations·filing 1980–2004
97Inventor score
Top patents by PatentIndex Score
25 records- 0183US4364074AV-MOS Device with self-aligned multiple electrodesIBM·Filed 1980·Granted Dec 14, 1982·53 cites·6 claims
- 0281US4531068ABus line precharging tristate driver circuitIBM·Filed 1983·Granted Jul 23, 1985·25 cites·6 claims
- 0378US6487134B2Single-event upset tolerant latch for sense amplifiersBAE SYSTEMS INFORMATION·Filed 2001·Granted Nov 26, 2002·28 cites·26 claims
- 0478US5822596AControlling power up using clock gatingIBM·Filed 1995·Granted Oct 13, 1998·35 cites·15 claims
- 0577US5524035ASymmetric clock system for a data processing system including dynamically switchable frequency dividerIBM·Filed 1995·Granted Jun 4, 1996·39 cites·7 claims
- 0674US5672991ADifferential delay line circuit for outputting signal with equal pulse widthsIBM·Filed 1996·Granted Sep 30, 1997·28 cites·17 claims
- 0764US5525914ACMOS driver circuitIBM·Filed 1995·Granted Jun 11, 1996·19 cites·25 claims
- 0864US5442776AElectronically tuneable computer clocking system and method of electronically tuning distribution lines of a computer clocking systemIBM·Filed 1994·Granted Aug 15, 1995·17 cites·1 claims
- 0964US4608649ADifferential cascode voltage switch (DCVS) master slice for high efficiency/custom density physical designIBM·Filed 1983·Granted Aug 26, 1986·12 cites·2 claims
- 1062US6642802B2Ring oscillator providing single event transient immunityBAE SYSTEMS INFORMATION·Filed 2001·Granted Nov 4, 2003·10 cites·22 claims
- 1159US5732233AHigh speed pipeline method and apparatusIBM·Filed 1995·Granted Mar 24, 1998·36 cites·15 claims
- 1257US4488067ATristate driver circuit with low standby power consumptionIBM·Filed 1983·Granted Dec 11, 1984·10 cites·10 claims
- 1355US5619158AHierarchical clocking system using adaptive feedbackIBM·Filed 1995·Granted Apr 8, 1997·33 cites·8 claims
- 1455US5272397ABasic DCVS circuits with dual function load circuitsIBM·Filed 1992·Granted Dec 21, 1993·13 cites·12 claims
- 1554US4484268AApparatus and method for decoding an operation code using a plurality of multiplexed programmable logic arraysTHOMA NANDOR G·Filed 1982·Granted Nov 20, 1984·21 cites·4 claims
- 1653US4500800ALogic performing cell for use in array structuresIBM·Filed 1982·Granted Feb 19, 1985·9 cites·4 claims
- 1752US5539333ACMOS receiver circuitIBM·Filed 1995·Granted Jul 23, 1996·29 cites·19 claims
- 1849US5299136AFully testable DCVS circuits with single-track global wiringIBM·Filed 1991·Granted Mar 29, 1994·15 cites·13 claims
- 1945US4575794AClocking mechanism for multiple overlapped dynamic programmable logic arrays used in a digital control unitIBM·Filed 1982·Granted Mar 11, 1986·13 cites·22 claims
- 2040US4947369AMicroword generation mechanism utilizing a separate branch decision programmable logic arrayIBM·Filed 1989·Granted Aug 7, 1990·9 cites·6 claims
- 2138US5166547AProgrammable DCVS logic circuitsIBM·Filed 1991·Granted Nov 24, 1992·12 cites·16 claims
- 2238US4567561ALarge scale integration data processor signal transfer mechanismIBM·Filed 1981·Granted Jan 28, 1986·10 cites·10 claims
- 2337US4395646ALogic performing cell for use in array structuresIBM·Filed 1980·Granted Jul 26, 1983·5 cites·6 claims
- 2433US4583193AIntegrated circuit mechanism for coupling multiple programmable logic arrays to a common busIBM·Filed 1982·Granted Apr 15, 1986·6 cites·10 claims
- 2531US2006133134A1Single-event upset tolerant static random access memory cellDOYLE SCOTT E·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →