Inventor · disambiguated record
Mark E. Bauer
Also filed as: BAUER MARK · BAUER MARK E
32 granted patents·2,575 citations·filing 1978–2008
98Inventor score
Top patents by PatentIndex Score
32 records- 0198US5539690AWrite verify schemes for flash memory with multilevel cellsINTEL CORP·Filed 1994·Granted Jul 23, 1996·314 cites·24 claims
- 0298US5508958AMethod and apparatus for sensing the state of floating gate memory cells by applying a variable gate voltageINTEL CORP·Filed 1994·Granted Apr 16, 1996·266 cites·26 claims
- 0397US5523972AMethod and apparatus for verifying the programming of multi-level flash EEPROM memoryINTEL CORP·Filed 1994·Granted Jun 4, 1996·277 cites·20 claims
- 0497US5485422ADrain bias multiplexing for multiple bit flash cellINTEL CORP·Filed 1994·Granted Jan 16, 1996·223 cites·43 claims
- 0596US6535423B2Drain bias for non-volatile memoryINTEL CORP·Filed 2000·Granted Mar 18, 2003·138 cites·35 claims
- 0696US5475693AError management processes for flash EEPROM memory arraysINTEL CORP·Filed 1994·Granted Dec 12, 1995·239 cites·18 claims
- 0794US5822256AMethod and circuitry for usage of partially functional nonvolatile memoryINTEL CORP·Filed 1997·Granted Oct 13, 1998·203 cites·52 claims
- 0893US6097637ADynamic single bit per cell to multiple bit per cell memoryINTEL CORP·Filed 1996·Granted Aug 1, 2000·109 cites·12 claims
- 0990US5497354ABit map addressing schemes for flash memoryINTEL CORP·Filed 1994·Granted Mar 5, 1996·56 cites·4 claims
- 1090US5444656AApparatus for fast internal reference cell trimmingINTEL CORP·Filed 1994·Granted Aug 22, 1995·85 cites·19 claims
- 1189US5828616ASensing scheme for flash memory with multilevel cellsINTEL CORP·Filed 1997·Granted Oct 27, 1998·71 cites·2 claims
- 1289US5046046ARedundancy CAM using word line from memoryINTEL CORP·Filed 1978·Granted Sep 3, 1991·44 cites·7 claims
- 1388US5438546AProgrammable redundancy scheme suitable for single-bit state and multibit state nonvolatile memoriesINTEL CORP·Filed 1994·Granted Aug 1, 1995·78 cites·15 claims
- 1487US5754566AMethod and apparatus for correcting a multilevel cell memory by using interleavingINTEL CORP·Filed 1996·Granted May 19, 1998·72 cites·23 claims
- 1587US5748546ASensing scheme for flash memory with multilevel cellsINTEL CORP·Filed 1997·Granted May 5, 1998·62 cites·3 claims
- 1684US6483742B1Bit map addressing schemes for flash memoryINTEL CORP·Filed 1996·Granted Nov 19, 2002·40 cites·17 claims
- 1783US5663923ANonvolatile memory blocking architectureINTEL CORP·Filed 1995·Granted Sep 2, 1997·61 cites·25 claims
- 1877US6772273B1Block-level read while write method and apparatusINTEL CORP·Filed 2000·Granted Aug 3, 2004·24 cites·16 claims
- 1976US6434049B1Sample and hold voltage reference sourceINTEL CORP·Filed 2000·Granted Aug 13, 2002·24 cites·22 claims
- 2076US5796667ABit map addressing schemes for flash memoryINTEL CORP·Filed 1996·Granted Aug 18, 1998·27 cites·6 claims
- 2174US5801991ADeselected word line that floats during MLC programming of a flash memoryINTEL CORP·Filed 1997·Granted Sep 1, 1998·37 cites·23 claims
- 2273US5781472ABit map addressing schemes for flash/memoryINTEL CORP·Filed 1997·Granted Jul 14, 1998·22 cites·5 claims
- 2372US5394037ASense amplifiers and sensing methodsLATTICE SEMICONDUCTOR CORP·Filed 1993·Granted Feb 28, 1995·24 cites·38 claims
- 2461US5274278AHigh-speed tri-level decoder with dual-voltage isolationINTEL CORP·Filed 1991·Granted Dec 28, 1993·21 cites·6 claims
- 2559US7751251B2Current sensing scheme for non-volatile memoryINTEL CORP·Filed 2008·Granted Jul 6, 2010·4 cites·19 claims
- 2657US5815443ABit map addressing schemes for flash memoryINTEL CORP·Filed 1996·Granted Sep 29, 1998·12 cites·2 claims
- 2752US5047989AChapter mode selection apparatus for MOS memoryINTEL CORP·Filed 1989·Granted Sep 10, 1991·21 cites·36 claims
- 2848US5517138ADual row selection using multiplexed tri-level decoderINTEL CORP·Filed 1994·Granted May 14, 1996·12 cites·4 claims
- 2942US6570789B2Load for non-volatile memory drain biasINTEL CORP·Filed 2000·Granted May 27, 2003·3 cites·20 claims
- 3041US6744671B2Kicker for non-volatile memory drain biasINTEL CORP·Filed 2000·Granted Jun 1, 2004·4 cites·20 claims
- 3139US6477086B2Local sensing of non-volatile memoryINTEL CORP·Filed 2000·Granted Nov 5, 2002·2 cites·31 claims
- 3236US7583559B2Two transistor wordline decoder output driverINTEL CORP·Filed 2007·Granted Sep 1, 2009·0 cites·7 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →