Inventor · disambiguated record
Ravi K. Bonam
Also filed as: BONAM RAVI K
20 granted patents·4 pending applications·36 citations·filing 2012–2023
91Inventor score
Top patents by PatentIndex Score
24 records- 0196US9929012B1Resist having tuned interface hardmask layer for EUV exposureIBM·Filed 2016·Granted Mar 27, 2018·20 cites·18 claims
- 0289US10943883B1Planar wafer level fan-out of multi-chip modules having different size chipsIBM·Filed 2019·Granted Mar 9, 2021·6 cites·20 claims
- 0381US11049844B2Semiconductor wafer having trenches with varied dimensions for multi-chip modulesIBM·Filed 2019·Granted Jun 29, 2021·3 cites·4 claims
- 0479US10991635B2Multiple chip bridge connectorIBM·Filed 2019·Granted Apr 27, 2021·2 cites·20 claims
- 0576US10725454B2Mask process aware calibration using mask pattern fidelity inspectionsIBM·Filed 2018·Granted Jul 28, 2020·1 cites·20 claims
- 0671US10937764B2Three-dimensional microelectronic package with embedded cooling channelsIBM·Filed 2019·Granted Mar 2, 2021·1 cites·17 claims
- 0770US11619877B2Determination of optical roughness in EUV structuresIBM·Filed 2022·Granted Apr 4, 2023·0 cites·20 claims
- 0870US9881762B2Integrated photoemission sources and scalable photoemission structuresIBM·Filed 2015·Granted Jan 30, 2018·1 cites·7 claims
- 0967US9263228B2Integrated photoemission sources and scalable photoemission structuresIBM·Filed 2014·Granted Feb 16, 2016·1 cites·13 claims
- 1066US11462512B2Three-dimensional microelectronic package with embedded cooling channelsIBM·Filed 2020·Granted Oct 4, 2022·0 cites·20 claims
- 1163US12086528B2Secure fingerprinting of a trusted photomaskIBM·Filed 2021·Granted Sep 10, 2024·0 cites·20 claims
- 1260US11887908B2Electronic package structure with offset stacked chips and top and bottom side cooling lidIBM·Filed 2021·Granted Jan 30, 2024·0 cites·20 claims
- 1359US10141188B2Resist having tuned interface hardmask layer for EUV exposureIBM·Filed 2017·Granted Nov 27, 2018·0 cites·20 claims
- 1459US10134592B2Resist having tuned interface hardmask layer for EUV exposureIBM·Filed 2017·Granted Nov 20, 2018·0 cites·20 claims
- 1559US2025201638A1Structure for monitoring hybrid bonds in a semiconductor chip packageIBM·Filed 2023·Application pending·0 cites
- 1658US2025149465A1Crackstop barrier architecture for hybrid bonded semiconductor packagesIBM·Filed 2023·Application pending·0 cites
- 1757US11480868B2Determination of optical roughness in EUV structuresIBM·Filed 2019·Granted Oct 25, 2022·0 cites·16 claims
- 1857US9177817B2Methods for fabricating three-dimensional nano-scale structures and devicesHARTLEY JOHN G·Filed 2012·Granted Nov 3, 2015·1 cites·38 claims
- 1956US11239167B2Cu—Cu bonding for interconnects on bridge chip attached to chips and packaging substrateIBM·Filed 2019·Granted Feb 1, 2022·0 cites·20 claims
- 2056US2025201775A1High capacitance hybrid bonded capacitor deviceIBM·Filed 2023·Application pending·0 cites
- 2154US11791270B2Direct bonded heterogeneous integration silicon bridgeIBM·Filed 2021·Granted Oct 17, 2023·0 cites·17 claims
- 2254US2025087629A1Dicing Street Design for Hybrid BondingIBM·Filed 2023·Application pending·0 cites
- 2349US11081424B2Micro-fluidic channels having various critical dimensionsIBM·Filed 2019·Granted Aug 3, 2021·0 cites·17 claims
- 2447US10437951B2Care area generation by detection optimized methodologyIBM·Filed 2017·Granted Oct 8, 2019·0 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →