Inventor · disambiguated record
Joanna Wasyluk
Also filed as: WASYLUK JOANNA
6 granted patents·3 pending applications·9 citations·filing 2012–2014
73Inventor score
Top patents by PatentIndex Score
9 records- 0172US9064961B2Integrated circuits including epitaxially grown strain-inducing fills doped with boron for improved robustness from delimination and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 23, 2015·3 cites·19 claims
- 0264US8703620B2Methods for PFET fabrication using APM solutionsWASYLUK JOANNA·Filed 2012·Granted Apr 22, 2014·2 cites·10 claims
- 0361US9018065B2Horizontal epitaxy furnace for channel SiGe formationWASYLUK JOANNA·Filed 2012·Granted Apr 28, 2015·2 cites·10 claims
- 0459US8658543B2Methods for pFET fabrication using APM solutionsWASYLUK JOANNA·Filed 2012·Granted Feb 25, 2014·2 cites·7 claims
- 0542US2016064513A1Integrated circuits with a bowed substrate, and methods for producing the sameGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 0640US9184260B2Methods for fabricating integrated circuits with robust gate electrode structure protectionGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 10, 2015·0 cites·18 claims
- 0738US8716102B2Methods of forming isolation structures for semiconductor devices by performing a dry chemical removal processJAKUBOWSKI FRANK·Filed 2012·Granted May 6, 2014·0 cites·13 claims
- 0836US2013299874A1Tmah recess for silicon germanium in positive channel region for cmos deviceWASYLUK JOANNA·Filed 2012·Application pending·0 cites
- 0936US2014187051A1Poly Removal for replacement gate with an APM mixtureINTERMOLECULAR INC·Filed 2012·Application pending·0 cites
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