Inventor · disambiguated record
Jayprakash Chipalkatti
Also filed as: CHIPALKATTI JAYPRAKASH · CHIPALKATTI JAYPRAKASH V · CHIPALKATTI JAYPRAKASH VIJAY
4 granted patents·4 pending applications·4 citations·filing 2007–2021
60Inventor score
Files withNVIDIA CORP4SAHASRABUDHE KAPIL HERAMB2CHIPALKATTI JAYPRAKASH VIJAY1JAVIER REYNALDO CORPUZ1
Top patents by PatentIndex Score
8 records- 0162US8102038B2Semiconductor chip attach configuration having improved thermal characteristicsSAHASRABUDHE KAPIL HERAMB·Filed 2009·Granted Jan 24, 2012·4 cites·21 claims
- 0260US11495568B2IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperaturesNVIDIA CORP·Filed 2021·Granted Nov 8, 2022·0 cites·14 claims
- 0349US10943882B1IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperaturesNVIDIA CORP·Filed 2019·Granted Mar 9, 2021·0 cites·7 claims
- 0444US10096534B2Thermal performance of logic chip in a package-on-package structureNVIDIA CORP·Filed 2012·Granted Oct 9, 2018·0 cites·20 claims
- 0542US2010289145A1Wafer chip scale package with center conductive massCHIPALKATTI JAYPRAKASH VIJAY·Filed 2009·Application pending·0 cites
- 0639US2009072373A1Packaged integrated circuits and methods to form a stacked integrated circuit packageJAVIER REYNALDO CORPUZ·Filed 2007·Application pending·0 cites
- 0738US2014133105A1Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structureNVIDIA CORP·Filed 2012·Application pending·0 cites
- 0837US2012094441A1Semiconductor Chip Attach Configuration Having Improved Thermal CharacteristicsSAHASRABUDHE KAPIL HERAMB·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →