Inventor · disambiguated record
Philip Alexander Cuadra
Also filed as: CUADRA PHILIP · CUADRA PHILIP ALEXANDER
18 granted patents·5 pending applications·46 citations·filing 2008–2021
91Inventor score
Top patents by PatentIndex Score
23 records- 0190US9513975B2Technique for computational nested parallelismJONES STEPHEN·Filed 2012·Granted Dec 6, 2016·13 cites·21 claims
- 0284US10552201B2Software-assisted instruction level execution preemptionNVIDIA CORP·Filed 2017·Granted Feb 4, 2020·3 cites·23 claims
- 0376US9507638B2Compute work distribution reference countersCUADRA PHILIP ALEXANDER·Filed 2011·Granted Nov 29, 2016·5 cites·20 claims
- 0475US8984183B2Signaling, ordering, and execution of dynamically generated tasks in a processing systemPURCELL TIMOTHY JOHN·Filed 2011·Granted Mar 17, 2015·4 cites·19 claims
- 0574US9542192B1Tokenized streams for concurrent execution between asymmetric multiprocessorsWILT NICHOLAS PATRICK·Filed 2008·Granted Jan 10, 2017·7 cites·14 claims
- 0673US10915364B2Technique for computational nested parallelismNVIDIA CORP·Filed 2016·Granted Feb 9, 2021·1 cites·27 claims
- 0773US9652282B2Software-assisted instruction level execution preemptionCUADRA PHILIP ALEXANDER·Filed 2011·Granted May 16, 2017·3 cites·20 claims
- 0872US9965321B2Error checking in out-of-order task schedulingDULUK JR JEROME F·Filed 2011·Granted May 8, 2018·3 cites·24 claims
- 0971US9448837B2Cooperative thread array granularity context switch during trap handlingNVIDIA CORP·Filed 2013·Granted Sep 20, 2016·2 cites·21 claims
- 1068US9710306B2Methods and apparatus for auto-throttling encapsulated compute tasksDULUK JR JEROME F·Filed 2012·Granted Jul 18, 2017·2 cites·22 claims
- 1167US9378139B2System, method, and computer program product for low latency scheduling and launch of memory defined tasksNVIDIA CORP·Filed 2013·Granted Jun 28, 2016·2 cites·20 claims
- 1267US2021349763A1Technique for computational nested parallelismNVIDIA CORP·Filed 2021·Application pending·0 cites
- 1367US2020151016A1Technique for computational nested parallelismNVIDIA CORP·Filed 2020·Application pending·0 cites
- 1458US10552202B2Software-assisted instruction level execution preemptionNVIDIA CORP·Filed 2017·Granted Feb 4, 2020·0 cites·23 claims
- 1558US10095542B2Cooperative thread array granularity context switch during trap handlingNVIDIA CORP·Filed 2017·Granted Oct 9, 2018·0 cites·23 claims
- 1656US9804885B2Cooperative thread array granularity context switch during trap handlingNVIDIA CORP·Filed 2016·Granted Oct 31, 2017·0 cites·21 claims
- 1752US8928677B2Low latency concurrent computationWEXLER DANIEL ELLIOT·Filed 2012·Granted Jan 6, 2015·1 cites·14 claims
- 1847US10235208B2Technique for saving and restoring thread group operating stateNVIDIA CORP·Filed 2012·Granted Mar 19, 2019·0 cites·28 claims
- 1946US9891949B2System and method for runtime scheduling of GPU tasksNVIDIA CORP·Filed 2013·Granted Feb 13, 2018·0 cites·26 claims
- 2044US10289418B2Cooperative thread array granularity context switch during trap handlingNVIDIA CORP·Filed 2012·Granted May 14, 2019·0 cites·24 claims
- 2139US2013198760A1Automatic dependent task launchCUADRA PHILIP ALEXANDER·Filed 2012·Application pending·0 cites
- 2236US2013124838A1Instruction level execution preemptionSHAH LACKY V·Filed 2011·Application pending·0 cites
- 2333US2013162661A1System and method for long running compute using buffers as timeslicesBOLZ JEFFREY A·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →