Inventor · disambiguated record
Theo Alan Drane
Also filed as: DRANE THEO · DRANE THEO ALAN
39 granted patents·30 pending applications·33 citations·filing 2004–2025
96Inventor score
Top patents by PatentIndex Score
69 records- 0194US10977000B2Partially and fully parallel normaliserIMAGINATION TECH LTD·Filed 2020·Granted Apr 13, 2021·3 cites·12 claims
- 0293US10223068B2Partially and fully parallel normaliserIMAGINATION TECH LTD·Filed 2017·Granted Mar 5, 2019·7 cites·14 claims
- 0390US9703525B2Partially and fully parallel normaliserIMAGINATION TECH LTD·Filed 2014·Granted Jul 11, 2017·8 cites·10 claims
- 0488US10698655B2Partially and fully parallel normaliserIMAGINATION TECH LTD·Filed 2019·Granted Jun 30, 2020·3 cites·18 claims
- 0582US2025060936A1Method and apparatus for use in the design and manufacture of integrated circuitsIMAGINATION TECH LTD·Filed 2024·Application pending·0 cites
- 0680US12353808B2Apparatus, device, method, and computer program for generating a register transfer level representation of a circuitINTEL CORP·Filed 2022·Granted Jul 8, 2025·1 cites·22 claims
- 0779US12169700B2Method and apparatus for use in the design and manufacture of integrated circuitsIMAGINATION TECH LTD·Filed 2023·Granted Dec 17, 2024·0 cites·16 claims
- 0879US12141548B2Trailing or leading digit anticipatorIMAGINATION TECH LTD·Filed 2023·Granted Nov 12, 2024·0 cites·18 claims
- 0973US11861323B2Partially and fully parallel normaliserIMAGINATION TECH LTD·Filed 2021·Granted Jan 2, 2024·0 cites·13 claims
- 1072US8381154B2Method of making apparatus for computing multiple sum of productsIMAGINATION TECH LTD·Filed 2011·Granted Feb 19, 2013·3 cites·10 claims
- 1171US11836460B2Error bounded multiplication by invariant rationalsIMAGINATION TECH LTD·Filed 2021·Granted Dec 5, 2023·0 cites·13 claims
- 1270US11669305B2Trailing or leading digit anticipatorIMAGINATION TECH LTD·Filed 2021·Granted Jun 6, 2023·0 cites·18 claims
- 1370US2025377875A1Automatic code generation of optimized rtl via redundant code removalINTEL CORP·Filed 2025·Application pending·0 cites
- 1468US12353862B2Automatic code generation of optimized RTL via redundant code removalINTEL CORP·Filed 2023·Granted Jul 8, 2025·0 cites·20 claims
- 1568US10949167B2Error bounded multiplication by invariant rationalsIMAGINATION TECH LTD·Filed 2020·Granted Mar 16, 2021·0 cites·11 claims
- 1668US8943447B2Method and apparatus for synthesising a sum of addends operation and an integrated circuitIMAGINATION TECH LTD·Filed 2013·Granted Jan 27, 2015·2 cites·12 claims
- 1767US10949169B2Trailing or leading digit anticipatorIMAGINATION TECH LTD·Filed 2020·Granted Mar 16, 2021·0 cites·20 claims
- 1867US2025284937A1Early exit for relu-based activationINTEL CORP·Filed 2024·Application pending·0 cites
- 1966US11748060B2Method and apparatus for use in the design and manufacture of integrated circuitsIMAGINATION TECH LTD·Filed 2019·Granted Sep 5, 2023·0 cites·9 claims
- 2065US11809795B2Implementing fixed-point polynomials in hardware logicIMAGINATION TECH LTD·Filed 2021·Granted Nov 7, 2023·0 cites·20 claims
- 2165US10606558B2Error bounded multiplication by invariant rationalsIMAGINATION TECH LTD·Filed 2019·Granted Mar 31, 2020·0 cites·14 claims
- 2264US10698660B2Trailing or leading digit anticipatorIMAGINATION TECH LTD·Filed 2019·Granted Jun 30, 2020·0 cites·18 claims
- 2364US8862652B2Method and apparatus for performing lossy integer multiplier synthesisDRANE THEO ALAN·Filed 2012·Granted Oct 14, 2014·2 cites·20 claims
- 2464US2024312034A1Level-of-detail determination using major squared and efficient clamping in a graphics environmentINTEL CORP·Filed 2023·Application pending·0 cites
- 2564US2024312110A1Level-of-detail eigenvector determination in a graphics environmentINTEL CORP·Filed 2023·Application pending·0 cites
- 2663US10540141B2Method and apparatus for use in the design and manufacture of integrated circuitsIMAGINATION TECH LTD·Filed 2018·Granted Jan 21, 2020·0 cites·20 claims
- 2763US2025291746A1Tensor Memory Accelerator EnhancementsINTEL CORP·Filed 2024·Application pending·0 cites
- 2862US10346137B2Trailing or leading digit anticipatorIMAGINATION TECH LTD·Filed 2018·Granted Jul 9, 2019·0 cites·19 claims
- 2962US10185545B2Trailing or leading zero counter having parallel and combinational logicIMAGINATION TECH LTD·Filed 2018·Granted Jan 22, 2019·0 cites·11 claims
- 3060US10310816B2Error bounded multiplication by invariant rationalsIMAGINATION TECH LTD·Filed 2017·Granted Jun 4, 2019·0 cites·15 claims
- 3160US10162600B2Method and apparatus for use in the design and manufacture of integrated circuitsIMAGINATION TECH LTD·Filed 2018·Granted Dec 25, 2018·0 cites·17 claims
- 3260US10042610B2Trailing or leading zero counter having parallel and combinational logicIMAGINATION TECH LTD·Filed 2017·Granted Aug 7, 2018·0 cites·14 claims
- 3360US2025284455A1Mixed format hardware and instructionINTEL CORP·Filed 2024·Application pending·0 cites
- 3460US2024126357A1Power optimized blendINTEL CORP·Filed 2023·Application pending·0 cites
- 3559US9830131B2Trailing or leading zero counter having parallel and combinational logicIMAGINATION TECH LTD·Filed 2017·Granted Nov 28, 2017·0 cites·11 claims
- 3657US10120651B2Trailing or leading digit anticipatorIMAGINATION TECH LTD·Filed 2016·Granted Nov 6, 2018·0 cites·13 claims
- 3757US9600240B2Trailing or leading zero counter having parallel and combinational logicIMAGINATION TECH LTD·Filed 2016·Granted Mar 21, 2017·0 cites·10 claims
- 3857US8527924B2Method and apparatus for performing formal verification of polynomial datapathDRANE THEO ALAN·Filed 2012·Granted Sep 3, 2013·1 cites·9 claims
- 3957US2024143279A1Floating-point n-input sum of squares 1ulp hardwareINTEL CORP·Filed 2023·Application pending·0 cites
- 4056US2024160407A1Integer square 1ulp hardware multiplierINTEL CORP·Filed 2023·Application pending·0 cites
- 4156US2024126967A1Semi-automatic tool to create formal verification modelsINTEL CORP·Filed 2023·Application pending·0 cites
- 4255US12079590B2Efficient dual-path floating-point arithmetic operatorsINTEL CORP·Filed 2020·Granted Sep 3, 2024·0 cites·19 claims
- 4355US2024134603A1Constant division and modulo via carrysave modulo reductionINTEL CORP·Filed 2023·Application pending·0 cites
- 4454US9424030B2Trailing or leading zero counter having parallel and combinational logicIMAGINATION TECH LTD·Filed 2015·Granted Aug 23, 2016·0 cites·11 claims
- 4554US2024311083A1Commutative 1ulp hardware multiplierINTEL CORP·Filed 2023·Application pending·0 cites
- 4653US2025335681A1Accelerating mutation testing for simulation and formal verificationINTEL CORP·Filed 2024·Application pending·0 cites
- 4752US11010515B2Implementing fixed-point polynomials in hardware logicIMAGINATION TECH LTD·Filed 2015·Granted May 18, 2021·0 cites·19 claims
- 4852US9933997B2Method and apparatus for use in the design and manufacture of integrated circuitsIMAGINATION TECH LTD·Filed 2012·Granted Apr 3, 2018·0 cites·19 claims
- 4951US2025348643A1Floating point compliance verificationINTEL CORP·Filed 2024·Application pending·0 cites
- 5050US2025291987A1Summarizing stimulus space via clustering and stochastic processesINTEL CORP·Filed 2024·Application pending·0 cites
Showing the top 50 of 69 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →