Inventor · disambiguated record
Bernd Hintze
Also filed as: HINTZE BERND
9 granted patents·4 pending applications·37 citations·filing 2005–2016
81Inventor score
Top patents by PatentIndex Score
13 records- 0194US9177858B1Methods for fabricating integrated circuits including barrier layers for interconnect structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 3, 2015·32 cites·20 claims
- 0264US9147618B2Method for detecting defects in a diffusion barrier layerGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 29, 2015·2 cites·20 claims
- 0356US9177826B2Methods of forming metal nitride materialsHINTZE BERND·Filed 2012·Granted Nov 3, 2015·1 cites·28 claims
- 0455US7416952B2Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayerINFINEON TECHNOLOGIES AG·Filed 2006·Granted Aug 26, 2008·1 cites·7 claims
- 0553US8138538B2Interconnect structure for semiconductor devicesMOLL HANS-PETER·Filed 2008·Granted Mar 20, 2012·1 cites·25 claims
- 0649US7880212B2Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayerQIMONDA AG·Filed 2008·Granted Feb 1, 2011·0 cites·4 claims
- 0745US7531418B2Method of producing a conductive layer including two metal nitridesQIMONDA AG·Filed 2005·Granted May 12, 2009·0 cites·19 claims
- 0841US10090195B2Method including a formation of a diffusion barrier and semiconductor structure including a diffusion barrierGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 2, 2018·0 cites·20 claims
- 0940US2014273436A1Methods of forming barrier layers for conductive copper structuresGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
- 1039US9171754B2Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean processGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 27, 2015·0 cites·28 claims
- 1136US2008282535A1Method of fabricating an integrated circuitQIMONDA AG·Filed 2007·Application pending·0 cites
- 1236US2014349479A1Method including a removal of a hardmask from a semiconductor structure and rinsing the semiconductor structure with an alkaline rinse solutionGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
- 1332US2014024213A1Processes for forming integrated circuits with post-patterning treamentHINTZE BERND·Filed 2012·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →