Inventor · disambiguated record
Robert F. Walker
Also filed as: WALKER ROBERT F · WALKER ROBERT FREDERIK
22 granted patents·3 pending applications·758 citations·filing 1982–2020
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
25 records- 0198US7484197B2Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designsIBM·Filed 2006·Granted Jan 27, 2009·297 cites·20 claims
- 0298US7302651B2Technology migration for integrated circuits with radical design restrictionsIBM·Filed 2004·Granted Nov 27, 2007·209 cites·39 claims
- 0397US7503020B2IC layout optimization to improve yieldIBM·Filed 2006·Granted Mar 10, 2009·110 cites·15 claims
- 0484US8464189B2Technology migration for integrated circuits with radical design restrictionsALLEN ROBERT J·Filed 2010·Granted Jun 11, 2013·6 cites·15 claims
- 0583US7761821B2Technology migration for integrated circuits with radical design restrictionsIBM·Filed 2007·Granted Jul 20, 2010·9 cites·24 claims
- 0680US7454721B2Method, apparatus and computer program product for optimizing an integrated circuit layoutIBM·Filed 2006·Granted Nov 18, 2008·11 cites·12 claims
- 0779US7882463B2Integrated circuit selective scalingIBM·Filed 2008·Granted Feb 1, 2011·8 cites·20 claims
- 0879US7610565B2Technology migration for integrated circuits with radical design restrictionsIBM·Filed 2007·Granted Oct 27, 2009·6 cites·15 claims
- 0976US7363601B2Integrated circuit selective scalingIBM·Filed 2004·Granted Apr 22, 2008·19 cites·10 claims
- 1073US7257783B2Technology migration for integrated circuits with radical design restrictionsIBM·Filed 2004·Granted Aug 14, 2007·12 cites·9 claims
- 1171US7062729B2Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimizationIBM·Filed 2004·Granted Jun 13, 2006·16 cites·17 claims
- 1270US7895562B2Adaptive weighting method for layout optimization with multiple prioritiesIBM·Filed 2007·Granted Feb 22, 2011·5 cites·6 claims
- 1370US7260790B2Integrated circuit yield enhancement using Voronoi diagramsIBM·Filed 2004·Granted Aug 21, 2007·15 cites·33 claims
- 1469US7735042B2Context aware sub-circuit layout modificationIBM·Filed 2007·Granted Jun 8, 2010·4 cites·20 claims
- 1565US7865848B2Layout optimization using parameterized cellsIBM·Filed 2007·Granted Jan 4, 2011·3 cites·2 claims
- 1664US7818694B2IC layout optimization to improve yieldIBM·Filed 2008·Granted Oct 19, 2010·2 cites·20 claims
- 1764US7568173B2Independent migration of hierarchical designs with methods of finding and fixing opens during migrationIBM·Filed 2007·Granted Jul 28, 2009·3 cites·12 claims
- 1861US7117456B2Circuit area minimization using scalingIBM·Filed 2003·Granted Oct 3, 2006·7 cites·20 claims
- 1957US7120887B2Cloned and original circuit shape mergingIBM·Filed 2004·Granted Oct 10, 2006·5 cites·20 claims
- 2048US7752589B2Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit designIBM·Filed 2007·Granted Jul 6, 2010·0 cites·32 claims
- 2144US2009037850A1Polygonal area design rule correction method for vlsi layoutsGRAY MICHAEL S·Filed 2007·Application pending·0 cites
- 2244US2008172638A1Method of optimizing hierarchical very large scale integration (vlsi) design by use of cluster-based logic cell cloningGRAY MICHAEL S·Filed 2007·Application pending·0 cites
- 2341US4516266AEntity control for raster displaysIBM·Filed 1982·Granted May 7, 1985·11 cites·8 claims
- 2439US2012233576A1Schematic-based layout migrationBARROWS GEOFFREY R·Filed 2011·Application pending·0 cites
- 2537US11567945B1Customized digital content generation systems and methodsPEGASYSTEMS INC·Filed 2020·Granted Jan 31, 2023·0 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →