Inventor · disambiguated record
Toshiaki Kirihata
Also filed as: KIRIHATA TOSHIAKI · KIRIHATA TOSHIAKI K
157 granted patents·5 pending applications·3,277 citations·filing 1991–2022
99Inventor score
Top patents by PatentIndex Score
162 records- 0196US5764655ABuilt in self test with memoryIBM·Filed 1997·Granted Jun 9, 1998·193 cites·30 claims
- 0295US9038133B2Self-authenticating of chip based on intrinsic featuresIBM·Filed 2012·Granted May 19, 2015·24 cites·16 claims
- 0395US9025386B1Embedded charge trap multi-time-programmable-read-only-memory for high performance logic technologyIBM·Filed 2013·Granted May 5, 2015·27 cites·20 claims
- 0495US5917744ASemiconductor memory having hierarchical bit line architecture with interleaved master bitlinesSIEMENS AG·Filed 1997·Granted Jun 29, 1999·142 cites·28 claims
- 0594US9690927B2Providing an authenticating service of a chipIBM·Filed 2015·Granted Jun 27, 2017·11 cites·20 claims
- 0694US9418745B1Rebalancing in twin cell memory schemes to enable multiple writesGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 16, 2016·19 cites·19 claims
- 0794US9208878B2Non-volatile memory based on retention modulationIBM·Filed 2014·Granted Dec 8, 2015·19 cites·20 claims
- 0894US7307911B1Apparatus and method for improving sensing margin of electrically programmable fusesIBM·Filed 2006·Granted Dec 11, 2007·30 cites·20 claims
- 0993US7145829B1Single cycle refresh of multi-port dynamic random access memory (DRAM)IBM·Filed 2005·Granted Dec 5, 2006·35 cites·20 claims
- 1093US5864496AHigh density semiconductor memory having diagonal bit lines and dual word linesSIEMENS AG·Filed 1997·Granted Jan 26, 1999·98 cites·19 claims
- 1192US9870979B2Double-sided segmented line architecture in 3D integrationIBM·Filed 2015·Granted Jan 16, 2018·10 cites·7 claims
- 1292US9559040B2Double-sided segmented line architecture in 3D integrationIBM·Filed 2013·Granted Jan 31, 2017·14 cites·10 claims
- 1392US9268863B2Hierarchical in-memory sort engineIBM·Filed 2014·Granted Feb 23, 2016·14 cites·20 claims
- 1492US7817455B2Random access electrically programmable e-fuse ROMIBM·Filed 2006·Granted Oct 19, 2010·31 cites·35 claims
- 1592US6038634AIntra-unit block addressing system for memoryIBM·Filed 1998·Granted Mar 14, 2000·112 cites·11 claims
- 1692US5822268AHierarchical column select line architecture for multi-bank DRAMsIBM·Filed 1997·Granted Oct 13, 1998·97 cites·19 claims
- 1791US8120968B2High voltage word line driverREOHR WILLIAM ROBERT·Filed 2010·Granted Feb 21, 2012·17 cites·22 claims
- 1891US7203794B2Destructive-read random access memory system buffered with destructive-read memory cacheIBM·Filed 2005·Granted Apr 10, 2007·21 cites·14 claims
- 1990US9659604B1Dual-bit 3-T high density MTPROM arrayGLOBALFOUNDRIES INC·Filed 2015·Granted May 23, 2017·14 cites·8 claims
- 2089US11417407B1Structures and methods of identifying unprogrammed bits for one-time-programmable-memory (OTPM)GLOBALFOUNDRIES US INC·Filed 2021·Granted Aug 16, 2022·2 cites·13 claims
- 2189US11380373B1Memory with read circuit for current-to-voltage slope characteristic-based sensing and methodGLOBALFOUNDRIES US INC·Filed 2021·Granted Jul 5, 2022·6 cites·20 claims
- 2289US9396143B2Hierarchical in-memory sort engineIBM·Filed 2015·Granted Jul 19, 2016·5 cites·13 claims
- 2389US6266272B1Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cellsIBM·Filed 1999·Granted Jul 24, 2001·78 cites·20 claims
- 2488US11056208B1Data dependent sense amplifier with symmetric marginingGLOBALFOUNDRIES US INC·Filed 2020·Granted Jul 6, 2021·3 cites·19 claims
- 2588US9460760B2Data-dependent self-biased differential sense amplifierGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 4, 2016·11 cites·25 claims
- 2688US9436845B2Physically unclonable fuse using a NOR type memory arrayGLOBALFOUNDRIES US 2 LLC·Filed 2014·Granted Sep 6, 2016·11 cites·7 claims
- 2788US6845033B2Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technologyIBM·Filed 2003·Granted Jan 18, 2005·46 cites·8 claims
- 2888US6141267ADefect management engine for semiconductor memories and memory systemsIBM·Filed 1999·Granted Oct 31, 2000·68 cites·53 claims
- 2988US5615164ALatched row decoder for a random access memoryIBM·Filed 1995·Granted Mar 25, 1997·70 cites·18 claims
- 3087US6522171B2Method of reducing sub-threshold leakage in circuits during standby modeIBM·Filed 2001·Granted Feb 18, 2003·33 cites·7 claims
- 3186US9202040B2Chip authentication using multi-domain intrinsic identifiersIBM·Filed 2012·Granted Dec 1, 2015·10 cites·20 claims
- 3286US6185712B1Chip performance optimization with self programmed built in self testIBM·Filed 1998·Granted Feb 6, 2001·68 cites·22 claims
- 3385US11329836B1Twin cell memory-based physically unclonable functionGLOBALFOUNDRIES US INC·Filed 2021·Granted May 10, 2022·2 cites·20 claims
- 3485US8590010B2Retention based intrinsic fingerprint identification featuring a fuzzy algorithm and a dynamic keyFAINSTEIN DANIEL J·Filed 2011·Granted Nov 19, 2013·15 cites·13 claims
- 3585US6950353B1Cell data margin test with dummy cellIBM·Filed 2005·Granted Sep 27, 2005·17 cites·20 claims
- 3685US6426914B1Floating wordline using a dynamic row decoder and bitline VDD prechargeIBM·Filed 2001·Granted Jul 30, 2002·37 cites·20 claims
- 3785US6243306B1Defect management engine for generating a unified address to access memory cells in a primary and a redundancy memory arrayIBM·Filed 2000·Granted Jun 5, 2001·37 cites·19 claims
- 3885US6178126B1Memory and system configuration for programming a redundancy address in an electric systemIBM·Filed 2000·Granted Jan 23, 2001·38 cites·32 claims
- 3985US6081021AConductor-insulator-conductor structureIBM·Filed 1998·Granted Jun 27, 2000·76 cites·14 claims
- 4084US9424308B2Hierarchical in-memory sort engineIBM·Filed 2016·Granted Aug 23, 2016·3 cites·1 claims
- 4184US7286437B2Three dimensional twisted bitline architecture for multi-port memoryIBM·Filed 2005·Granted Oct 23, 2007·11 cites·15 claims
- 4283US6967885B2Concurrent refresh mode with distributed row address counters in an embedded DRAMIBM·Filed 2004·Granted Nov 22, 2005·33 cites·16 claims
- 4383US6845059B1High performance gain cell architectureIBM·Filed 2003·Granted Jan 18, 2005·34 cites·23 claims
- 4483US6747890B1Gain cell structure with deep trench capacitorIBM·Filed 2003·Granted Jun 8, 2004·35 cites·10 claims
- 4583US6230290B1Method of self programmed built in self testIBM·Filed 1997·Granted May 8, 2001·54 cites·20 claims
- 4683US5499211ABit-line precharge current limiter for CMOS dynamic memoriesIBM·Filed 1995·Granted Mar 12, 1996·57 cites·8 claims
- 4782US9431339B2Wiring structure for trench fuse component with methods of fabricationIBM·Filed 2014·Granted Aug 30, 2016·5 cites·20 claims
- 4882US6990025B2Multi-port memory architectureIBM·Filed 2003·Granted Jan 24, 2006·31 cites·18 claims
- 4981US5949732AMethod of structuring a multi-bank DRAM into a hierarchical column select line architectureIBM·Filed 1997·Granted Sep 7, 1999·47 cites·19 claims
- 5080US6272062B1Semiconductor memory with programmable bitline multiplexersINFINEON TECHNOLOGIES AG·Filed 2000·Granted Aug 7, 2001·29 cites·31 claims
Showing the top 50 of 162 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →