Inventor · disambiguated record
Janakiraman Viraraghavan
Also filed as: VIRARAGHAVAN JANAKIRAMAN
9 granted patents·35 citations·filing 2013–2017
84Inventor score
Top patents by PatentIndex Score
9 records- 0190US9659604B1Dual-bit 3-T high density MTPROM arrayGLOBALFOUNDRIES INC·Filed 2015·Granted May 23, 2017·14 cites·8 claims
- 0281US9292652B2Generic design rule checking (DRC) test case extractionIBM·Filed 2014·Granted Mar 22, 2016·6 cites·19 claims
- 0378US9721059B1Post-layout thermal-aware integrated circuit performance modelingGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 1, 2017·4 cites·17 claims
- 0478US8875064B2Automated design rule checking (DRC) test case generationIBM·Filed 2013·Granted Oct 28, 2014·5 cites·16 claims
- 0574US9859177B2Test method and structure for integrated circuits before complete metalizationGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 2, 2018·2 cites·16 claims
- 0668US9589658B1Disturb free bitcell and arrayGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 7, 2017·3 cites·20 claims
- 0755US9721673B1Distributed current source/sink using inactive memory elementsGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 1, 2017·1 cites·20 claims
- 0849US9990458B2Generic design rule checking (DRC) test case extractionIBM·Filed 2016·Granted Jun 5, 2018·0 cites·16 claims
- 0944US9786333B2Dual-bit 3-T high density MTPROM arrayGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 10, 2017·0 cites·8 claims
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