Inventor · disambiguated record
Scott Dion Rodgers
Also filed as: RODGERS SCOTT · RODGERS SCOTT D · RODGERS SCOTT D DION · RODGERS SCOTT DION
84 granted patents·5 pending applications·1,112 citations·filing 1993–2021
99Inventor score
Top patents by PatentIndex Score
89 records- 0196US8230120B2PCI express enhancements and extensionsAJANOVIC JASMIN·Filed 2011·Granted Jul 24, 2012·21 cites·28 claims
- 0296US7949794B2PCI express enhancements and extensionsINTEL CORP·Filed 2006·Granted May 24, 2011·41 cites·22 claims
- 0394US8230119B2PCI express enhancements and extensionsAJANOVIC JASMIN·Filed 2010·Granted Jul 24, 2012·14 cites·3 claims
- 0494US8099523B2PCI express enhancements and extensions including transactions having prefetch parametersAJANOVIC JASMIN·Filed 2011·Granted Jan 17, 2012·16 cites·4 claims
- 0593US7899943B2PCI express enhancements and extensionsINTEL CORP·Filed 2007·Granted Mar 1, 2011·16 cites·23 claims
- 0692US8073981B2PCI express enhancements and extensionsAJANOVIC JASMIN·Filed 2007·Granted Dec 6, 2011·14 cites·12 claims
- 0792US7430578B2Method and apparatus for performing multiply-add operations on packed byte dataINTEL CORP·Filed 2003·Granted Sep 30, 2008·98 cites·32 claims
- 0891US8549183B2PCI express enhancements and extensionsAJANOVIC JASMIN·Filed 2010·Granted Oct 1, 2013·8 cites·22 claims
- 0991US8464035B2Instruction for enabling a processor wait stateDIXON MARTIN G·Filed 2009·Granted Jun 11, 2013·23 cites·24 claims
- 1091US8447888B2PCI express enhancements and extensionsAJANOVIC JASMIN·Filed 2011·Granted May 21, 2013·8 cites·15 claims
- 1191US7930566B2PCI express enhancements and extensionsINTEL CORP·Filed 2007·Granted Apr 19, 2011·13 cites·17 claims
- 1290US8793470B2Length determination of instruction code with address form field and escape opcode value by evaluating portions other than instruction specific opcodeINTEL CORP·Filed 2013·Granted Jul 29, 2014·9 cites·20 claims
- 1390US8555101B2PCI express enhancements and extensionsAJANOVIC JASMIN·Filed 2011·Granted Oct 8, 2013·7 cites·10 claims
- 1489US8473642B2PCI express enhancements and extensions including device window cachingAJANOVIC JASMIN·Filed 2011·Granted Jun 25, 2013·6 cites·12 claims
- 1588US9990206B2Mechanism for instruction set based thread execution of a plurality of instruction sequencersINTEL CORP·Filed 2013·Granted Jun 5, 2018·8 cites·18 claims
- 1688US9032103B2Transaction re-orderingINTEL CORP·Filed 2012·Granted May 12, 2015·5 cites·27 claims
- 1788US9026682B2Prefectching in PCI expressINTEL CORP·Filed 2012·Granted May 5, 2015·5 cites·35 claims
- 1888US8793404B2Atomic operationsAJANOVIC JASMIN·Filed 2012·Granted Jul 29, 2014·5 cites·6 claims
- 1987US9098415B2PCI express transaction descriptorINTEL CORP·Filed 2012·Granted Aug 4, 2015·4 cites·39 claims
- 2086US9405570B2Low latency virtual machine page table managementSAHITA RAVI L·Filed 2011·Granted Aug 2, 2016·9 cites·3 claims
- 2186US7849465B2Programmable event driven yield mechanism which may activate service threadsINTEL CORP·Filed 2005·Granted Dec 7, 2010·18 cites·24 claims
- 2285US8762694B1Programmable event-driven yield mechanismZOU XIANG·Filed 2006·Granted Jun 24, 2014·24 cites·26 claims
- 2385US7743233B2Sequencer address managementINTEL CORP·Filed 2005·Granted Jun 22, 2010·15 cites·21 claims
- 2485US5889982AMethod and apparatus for generating event handler vectors based on both operating mode and event typeINTEL CORP·Filed 1995·Granted Mar 30, 1999·129 cites·67 claims
- 2584US8561068B2Optimizing processor-managed resources based on the behavior of a virtual machine monitorBENNETT STEVEN M·Filed 2011·Granted Oct 15, 2013·6 cites·16 claims
- 2682US5517651AMethod and apparatus for loading a segment register in a microprocessor capable of operating in multiple modesINTEL CORP·Filed 1993·Granted May 14, 1996·97 cites·39 claims
- 2781US8601233B2Synchronizing a translation lookaside buffer with an extended paging tableBENNETT STEVEN M·Filed 2012·Granted Dec 3, 2013·2 cites·17 claims
- 2881US7424709B2Use of multiple virtual machine monitors to handle privileged eventsINTEL CORP·Filed 2003·Granted Sep 9, 2008·30 cites·29 claims
- 2980US9535838B2Atomic operations in PCI expressINTEL CORP·Filed 2012·Granted Jan 3, 2017·2 cites·25 claims
- 3080US7448025B2Qualification of event detection by thread ID and thread privilege levelINTEL CORP·Filed 2000·Granted Nov 4, 2008·35 cites·28 claims
- 3179US8635415B2Managing and implementing metadata in central processing unit using register extensionsPATEL BAIJU V·Filed 2009·Granted Jan 21, 2014·11 cites·13 claims
- 3279US7966476B2Determining length of instruction with escape and addressing form bytes without evaluating opcodeINTEL CORP·Filed 2008·Granted Jun 21, 2011·6 cites·30 claims
- 3378US9372807B2Synchronizing a translation lookaside buffer with an extended paging tableINTEL CORP·Filed 2015·Granted Jun 21, 2016·1 cites·6 claims
- 3478US8990597B2Instruction for enabling a processor wait stateINTEL CORP·Filed 2013·Granted Mar 24, 2015·3 cites·20 claims
- 3576US9442855B2Transaction layer packet formattingINTEL CORP·Filed 2014·Granted Sep 13, 2016·1 cites·27 claims
- 3676US8214598B2System, method, and apparatus for a cache flush of a range of pages and TLB invalidation of a range of entriesDIXON MARTIN G·Filed 2009·Granted Jul 3, 2012·7 cites·13 claims
- 3774US9430384B2Instructions and logic to provide advanced paging capabilities for secure enclave page cachesROZAS CARLOS V·Filed 2013·Granted Aug 30, 2016·3 cites·28 claims
- 3874US9164920B2Using permission bits in translating guests virtual addresses to guest physical addresses to host physical addressesINTEL CORP·Filed 2014·Granted Oct 20, 2015·2 cites·17 claims
- 3974US8079034B2Optimizing processor-managed resources based on the behavior of a virtual machine monitorBENNETT STEVEN M·Filed 2003·Granted Dec 13, 2011·15 cites·6 claims
- 4073US8719819B2Mechanism for instruction set based thread execution on a plurality of instruction sequencersWANG HONG·Filed 2005·Granted May 6, 2014·4 cites·20 claims
- 4172US9405937B2Method and apparatus for securing a dynamic binary translation systemINTEL CORP·Filed 2013·Granted Aug 2, 2016·3 cites·24 claims
- 4272US5625788AMicroprocessor with novel instruction for signaling event occurrence and for providing event handling information in response theretoINTEL CORP·Filed 1994·Granted Apr 29, 1997·56 cites·16 claims
- 4372US5517657ASegment register file read and write pipelineINTEL CORP·Filed 1994·Granted May 14, 1996·58 cites·52 claims
- 4471US10592421B2Instructions and logic to provide advanced paging capabilities for secure enclave page cachesINTEL CORP·Filed 2016·Granted Mar 17, 2020·1 cites·11 claims
- 4571US8402252B2Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcodeCOKE JAMES S·Filed 2012·Granted Mar 19, 2013·2 cites·19 claims
- 4671US7287197B2Vectoring an interrupt or exception upon resuming operation of a virtual machineINTEL CORP·Filed 2003·Granted Oct 23, 2007·15 cites·26 claims
- 4771US5636374AMethod and apparatus for performing operations based upon the addresses of microinstructionsINTEL CORP·Filed 1995·Granted Jun 3, 1997·68 cites·48 claims
- 4870US11683310B2Protecting supervisor mode informationINTEL CORP·Filed 2021·Granted Jun 20, 2023·0 cites·30 claims
- 4970US10747682B2Synchronizing a translation lookaside buffer with an extended paging tableINTEL CORP·Filed 2018·Granted Aug 18, 2020·0 cites·10 claims
- 5070US9405551B2Creating an isolated execution environment in a co-designed processorINTEL CORP·Filed 2013·Granted Aug 2, 2016·3 cites·19 claims
Showing the top 50 of 89 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Scott Dion Rodgers files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →