Inventor · disambiguated record
John Erik Lindholm
Also filed as: LINDHOLM JOHN E · LINDHOLM JOHN ERIK
126 granted patents·5 pending applications·3,991 citations·filing 1999–2019
99Inventor score
Top patents by PatentIndex Score
131 records- 0199US9569559B2Beam tracingNVIDIA CORP·Filed 2015·Granted Feb 14, 2017·67 cites·16 claims
- 0298US7634637B1Execution of parallel groups of threads with per-instruction serializationNVIDIA CORP·Filed 2005·Granted Dec 15, 2009·126 cites·16 claims
- 0398US7353369B1System and method for managing divergent threads in a SIMD architectureNVIDIA CORP·Filed 2005·Granted Apr 1, 2008·96 cites·15 claims
- 0498US7015913B1Method and apparatus for multithreaded processing of data in a programmable graphics processorNVIDIA CORP·Filed 2003·Granted Mar 21, 2006·224 cites·33 claims
- 0598US6947047B1Method and system for programmable pipelined graphics processing with branching instructionsNVIDIA CORP·Filed 2002·Granted Sep 20, 2005·182 cites·47 claims
- 0697US7617384B1Structured programming control flow using a disable mask in a SIMD architectureNVIDIA CORP·Filed 2007·Granted Nov 10, 2009·83 cites·20 claims
- 0797US7038685B1Programmable graphics processor for multithreaded execution of programsNVIDIA CORP·Filed 2003·Granted May 2, 2006·128 cites·45 claims
- 0896US8976195B1Generating clip state for a batch of verticesLINDHOLM JOHN ERIK·Filed 2009·Granted Mar 10, 2015·53 cites·26 claims
- 0996US8087029B1Thread-type-based load balancing in a multithreaded processorLINDHOLM JOHN ERIK·Filed 2006·Granted Dec 27, 2011·68 cites·12 claims
- 1096US7366878B1Scheduling instructions from multi-thread instruction buffer based on phase boundary qualifying rule for phases of math and data access operations with better cachingNVIDIA CORP·Filed 2006·Granted Apr 29, 2008·47 cites·20 claims
- 1196US6992667B2Single semiconductor graphics platform system and method with skinning, swizzling and masking capabilitiesNVIDIA CORP·Filed 2003·Granted Jan 31, 2006·75 cites·29 claims
- 1296US6724394B1Programmable pixel shading architectureNVIDIA CORP·Filed 2001·Granted Apr 20, 2004·139 cites·17 claims
- 1396US6577309B2System and method for a graphics processing framework embodied utilizing a single semiconductor platformNVIDIA CORP·Filed 2001·Granted Jun 10, 2003·72 cites·44 claims
- 1496US6198488B1Transform, lighting and rasterization system embodied on a single semiconductor platformNVIDIA CORP·Filed 1999·Granted Mar 6, 2001·133 cites·26 claims
- 1595US9519947B2Architecture and instructions for accessing multi-dimensional formatted surface memoryNICKOLLS JOHN R·Filed 2010·Granted Dec 13, 2016·33 cites·27 claims
- 1695US8502819B1System and method for performing ray tracing node traversal in image renderingAILA TIMO·Filed 2010·Granted Aug 6, 2013·31 cites·24 claims
- 1795US8200940B1Reduction operations in a synchronous parallel thread processing system with disabled execution threadsLINDHOLM JOHN ERIK·Filed 2008·Granted Jun 12, 2012·49 cites·20 claims
- 1895US8108872B1Thread-type-based resource allocation in a multithreaded processorLINDHOLM JOHN ERIK·Filed 2006·Granted Jan 31, 2012·44 cites·18 claims
- 1995US7877585B1Structured programming control flow in a SIMD architectureNVIDIA CORP·Filed 2007·Granted Jan 25, 2011·47 cites·20 claims
- 2095US7761697B1Processing an indirect branch instruction in a SIMD architectureNVIDIA CORP·Filed 2006·Granted Jul 20, 2010·52 cites·20 claims
- 2195US7676657B2Across-thread out-of-order instruction dispatch in a multithreaded microprocessorNVIDIA CORP·Filed 2006·Granted Mar 9, 2010·35 cites·19 claims
- 2295US7634621B1Register file allocationNVIDIA CORP·Filed 2006·Granted Dec 15, 2009·45 cites·24 claims
- 2395US7543136B1System and method for managing divergent threads using synchronization tokens and program instructions that include set-synchronization bitsNVIDIA CORP·Filed 2005·Granted Jun 2, 2009·45 cites·19 claims
- 2495US7064763B2Single semiconductor graphics platformNVIDIA CORP·Filed 2002·Granted Jun 20, 2006·64 cites·52 claims
- 2595US6734874B2Graphics processing unit with transform module capable of handling scalars and vectorsNVIDIA CORP·Filed 2001·Granted May 11, 2004·82 cites·30 claims
- 2694US7002588B1System, method and computer program product for branching during programmable vertex processingNVIDIA CORP·Filed 2003·Granted Feb 21, 2006·76 cites·21 claims
- 2794US6731298B1System, method and article of manufacture for z-texture mappingNVIDIA CORP·Filed 2000·Granted May 4, 2004·85 cites·24 claims
- 2893US8564616B1Cull before vertex attribute fetch and vertex lightingHAKURA ZIYAD S·Filed 2009·Granted Oct 22, 2013·14 cites·20 claims
- 2993US8542247B1Cull before vertex attribute fetch and vertex lightingHAKURA ZIYAD S·Filed 2009·Granted Sep 24, 2013·33 cites·22 claims
- 3093US7310722B2Across-thread out of order instruction dispatch in a multithreaded graphics processorNVIDIA CORP·Filed 2003·Granted Dec 18, 2007·68 cites·23 claims
- 3193US6870540B1System, method and computer program product for a programmable pixel processing model with instruction setNVIDIA CORP·Filed 2001·Granted Mar 22, 2005·77 cites·32 claims
- 3293US6650330B2Graphics system and method for processing multiple independent execution threadsNVIDIA CORP·Filed 2002·Granted Nov 18, 2003·70 cites·23 claims
- 3393US6462737B2Clipping system and method for a graphics processing framework embodied on a single semiconductor platformNVIDIA CORP·Filed 2001·Granted Oct 8, 2002·48 cites·18 claims
- 3492US7095414B2Blending system and method in an integrated computer graphics pipelineNVIDIA CORP·Filed 2002·Granted Aug 22, 2006·54 cites·30 claims
- 3592US7009607B2Method, apparatus and article of manufacture for a transform module in a graphics processorNVIDIA CORP·Filed 2001·Granted Mar 7, 2006·42 cites·31 claims
- 3692US6894687B1System, method and computer program product for vertex attribute aliasing in a graphics pipelineNVIDIA CORP·Filed 2001·Granted May 17, 2005·73 cites·7 claims
- 3792US6828980B1System, method and computer program product for z-texture mappingNVIDIA CORP·Filed 2003·Granted Dec 7, 2004·56 cites·34 claims
- 3892US6650331B2System, method and computer program product for performing a scissor operation in a graphics processing framework embodied on a single semiconductor platformNVIDIA CORP·Filed 2001·Granted Nov 18, 2003·43 cites·49 claims
- 3991US7564456B1Apparatus and method for raster tile coalescingNVIDIA CORP·Filed 2006·Granted Jul 21, 2009·27 cites·18 claims
- 4091US7542043B1Subdividing a shader programNVIDIA CORP·Filed 2005·Granted Jun 2, 2009·24 cites·17 claims
- 4191US7233335B2System and method for reserving and managing memory spaces in a memory resourceNVIDIA CORP·Filed 2003·Granted Jun 19, 2007·57 cites·50 claims
- 4291US6987517B1Programmable graphics processor for generalized texturingNVIDIA CORP·Filed 2004·Granted Jan 17, 2006·50 cites·20 claims
- 4391US6778176B2Sequencer system and method for sequencing graphics processingNVIDIA CORP·Filed 2002·Granted Aug 17, 2004·53 cites·11 claims
- 4490US9442755B2System and method for hardware scheduling of indexed barriersNVIDIA CORP·Filed 2013·Granted Sep 13, 2016·14 cites·20 claims
- 4590US8730249B2Parallel array architecture for a graphics processorDANSKIN JOHN M·Filed 2011·Granted May 20, 2014·6 cites·17 claims
- 4690US8732713B2Thread group scheduler for computing on a parallel thread processorCOON BRETT W·Filed 2011·Granted May 20, 2014·15 cites·20 claims
- 4790US7834881B2Operand collector architectureNVIDIA CORP·Filed 2006·Granted Nov 16, 2010·22 cites·20 claims
- 4889US10242485B2Beam tracingNVIDIA CORP·Filed 2016·Granted Mar 26, 2019·7 cites·19 claims
- 4989US8564589B1System and method for accelerated ray-box intersection testingAILA TIMO·Filed 2010·Granted Oct 22, 2013·13 cites·16 claims
- 5089US8174531B1Programmable graphics processor for multithreaded execution of programsLINDHOLM JOHN ERIK·Filed 2009·Granted May 8, 2012·16 cites·10 claims
Showing the top 50 of 131 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →