Inventor · disambiguated record
Ted R. White
Also filed as: WHITE TED R
43 granted patents·4 pending applications·1,274 citations·filing 1987–2012
98Inventor score
Top patents by PatentIndex Score
47 records- 0198US6838322B2Method for forming a double-gated semiconductor deviceFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Jan 4, 2005·259 cites·21 claims
- 0297US7282402B2Method of making a dual strained channel semiconductor deviceFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Oct 16, 2007·69 cites·19 claims
- 0397US7226833B2Semiconductor device structure and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jun 5, 2007·124 cites·18 claims
- 0496US7494856B2Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressorFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Feb 24, 2009·51 cites·20 claims
- 0596US7074664B1Dual metal gate electrode semiconductor fabrication process and structure thereofFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jul 11, 2006·49 cites·7 claims
- 0695US7018901B1Method for forming a semiconductor device having a strained channel and a heterojunction source/drainFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Mar 28, 2006·105 cites·24 claims
- 0794US6831350B1Semiconductor structure with different lattice constant materials and method for forming the sameFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Dec 14, 2004·89 cites·21 claims
- 0893US7226820B2Transistor fabrication using double etch/refill processFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jun 5, 2007·34 cites·20 claims
- 0992US7524707B2Modified hybrid orientation technologyFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Apr 28, 2009·19 cites·15 claims
- 1092US7288458B2SOI active layer with different surface orientationFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Oct 30, 2007·21 cites·21 claims
- 1189US7803670B2Twisted dual-substrate orientation (DSO) substratesFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Sep 28, 2010·19 cites·19 claims
- 1288US8163615B1Split-gate non-volatile memory cell having improved overlap tolerance and method thereforWHITE TED R·Filed 2011·Granted Apr 24, 2012·11 cites·17 claims
- 1387US7265004B2Electronic devices including a semiconductor layer and a process for forming the sameFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Sep 4, 2007·15 cites·14 claims
- 1487US7067868B2Double gate device having a heterojunction source/drain and strained channelFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jun 27, 2006·39 cites·17 claims
- 1586US7029980B2Method of manufacturing SOI template layerFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Apr 18, 2006·25 cites·17 claims
- 1686US5918147AProcess for forming a semiconductor device with an antireflective layerMOTOROLA INC·Filed 1995·Granted Jun 29, 1999·89 cites·42 claims
- 1783US7821067B2Electronic devices including a semiconductor layerFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Oct 26, 2010·11 cites·20 claims
- 1881US7208357B2Template layer formationFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Apr 24, 2007·18 cites·26 claims
- 1980US8426310B2Method of forming a shared contact in a semiconductor deviceADETUTU OLUBUNMI O·Filed 2010·Granted Apr 23, 2013·6 cites·20 claims
- 2080US7037795B1Low RC product transistors in SOI semiconductor processFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted May 2, 2006·26 cites·17 claims
- 2180US5589423AProcess for fabricating a non-silicided region in an integrated circuitMOTOROLA INC·Filed 1994·Granted Dec 31, 1996·55 cites·16 claims
- 2275US8125032B2Modified hybrid orientation technologyADETUTU OLUBUNMI O·Filed 2009·Granted Feb 28, 2012·5 cites·20 claims
- 2375US7749829B2Step height reduction between SOI and EPI for DSO and BOS integrationFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jul 6, 2010·7 cites·22 claims
- 2475US7556992B2Method for forming vertical structures in a semiconductor deviceFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jul 7, 2009·6 cites·22 claims
- 2575US7544548B2Trench liner for DSO integrationFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jun 9, 2009·6 cites·22 claims
- 2672US8390026B2Electronic device including a heterojunction regionWINSTEAD BRIAN A·Filed 2006·Granted Mar 5, 2013·5 cites·20 claims
- 2772US7781840B2Semiconductor device structureFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Aug 24, 2010·4 cites·6 claims
- 2870US7205210B2Semiconductor structure having strained semiconductor and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Apr 17, 2007·16 cites·15 claims
- 2970US7163903B2Method for making a semiconductor structure using silicon germaniumFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jan 16, 2007·10 cites·21 claims
- 3069US7402477B2Method of making a multiple crystal orientation semiconductor deviceFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jul 22, 2008·4 cites·16 claims
- 3167US7799644B2Transistor with asymmetry for data storage circuitryFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Sep 21, 2010·3 cites·17 claims
- 3267US7285452B2Method to selectively form regions having differing properties and structureSADAKA MARIAM G·Filed 2006·Granted Oct 23, 2007·4 cites·13 claims
- 3367US4902533AMethod for selectively depositing tungsten on a substrate by using a spin-on metal oxideMOTOROLA INC·Filed 1987·Granted Feb 20, 1990·39 cites·8 claims
- 3466US7700420B2Integrated circuit with different channel materials for P and N channel transistors and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Apr 20, 2010·3 cites·9 claims
- 3564US7923328B2Split gate non-volatile memory cell with improved endurance and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Apr 12, 2011·2 cites·10 claims
- 3664US7056778B2Semiconductor layer formationFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jun 6, 2006·7 cites·42 claims
- 3763US7160769B2Channel orientation to enhance transistor performanceFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jan 9, 2007·10 cites·24 claims
- 3862US7923769B2Split gate non-volatile memory cell with improved endurance and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2010·Granted Apr 12, 2011·1 cites·9 claims
- 3961US7811382B2Method for forming a semiconductor structure having a strained silicon layerFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Oct 12, 2010·1 cites·15 claims
- 4060US7479422B2Semiconductor device with stressors and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jan 20, 2009·2 cites·7 claims
- 4157US7241647B2Graded semiconductor layerFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jul 10, 2007·5 cites·29 claims
- 4253US7927956B2Method for making a semiconductor structure using silicon germaniumFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Apr 19, 2011·0 cites·6 claims
- 4347US9111908B2Split-gate non-volatile memory cells having improved overlap toleranceWHITE TED R·Filed 2012·Granted Aug 18, 2015·0 cites·11 claims
- 4439US2007257322A1Hybrid Transistor Structure and a Method for Making the SameFREESCALE SEMICONDUCTOR INC·Filed 2006·Application pending·0 cites
- 4535US2006228872A1Method of making a semiconductor device having an arched structure strained semiconductor layerNGUYEN BICH-YEN·Filed 2005·Application pending·0 cites
- 4635US2006226492A1Semiconductor device featuring an arched structure strained semiconductor layerNGUYEN BICH-YEN·Filed 2005·Application pending·0 cites
- 4734US2006030093A1Strained semiconductor devices and method for forming at least a portion thereofZHANG DA·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →