Inventor · disambiguated record
Darren M. Jones
Also filed as: JONES DARREN · JONES DARREN M · JONES DARREN MILLER
28 granted patents·752 citations·filing 1995–2011
97Inventor score
Top patents by PatentIndex Score
28 records- 0195US6754804B1Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructionsMIPS TECH INC·Filed 2000·Granted Jun 22, 2004·130 cites·25 claims
- 0294US7853777B2Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructionsMIPS TECH INC·Filed 2005·Granted Dec 14, 2010·43 cites·38 claims
- 0394US7424599B2Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessorMIPS TECH INC·Filed 2004·Granted Sep 9, 2008·63 cites·57 claims
- 0493US6742165B2System, method and computer program product for web-based integrated circuit designMIPS TECH INC·Filed 2001·Granted May 25, 2004·108 cites·22 claims
- 0592US7752627B2Leaky-bucket thread scheduler in a multithreading microprocessorMIPS TECH INC·Filed 2005·Granted Jul 6, 2010·34 cites·39 claims
- 0692US7627770B2Apparatus and method for automatic low power mode invocation in a multi-threaded processorMIPS TECH INC·Filed 2005·Granted Dec 1, 2009·27 cites·8 claims
- 0790US7664936B2Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stagesMIPS TECH INC·Filed 2005·Granted Feb 16, 2010·26 cites·72 claims
- 0888US7657891B2Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiencyMIPS TECH INC·Filed 2005·Granted Feb 2, 2010·18 cites·39 claims
- 0988US7600135B2Apparatus and method for software specified power management performance using low power virtual threadsMIPS TECH INC·Filed 2005·Granted Oct 6, 2009·19 cites·22 claims
- 1088US7194599B2Configurable co-processor interfaceMIPS TECH INC·Filed 2006·Granted Mar 20, 2007·14 cites·3 claims
- 1184US7613904B2Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal schedulerMIPS TECH INC·Filed 2005·Granted Nov 3, 2009·14 cites·91 claims
- 1284US7168066B1Tracing out-of order load dataMIPS TECH INC·Filed 2001·Granted Jan 23, 2007·38 cites·23 claims
- 1383US7287147B1Configurable co-processor interfaceMIPS TECH INC·Filed 2000·Granted Oct 23, 2007·26 cites·15 claims
- 1479US8151268B2Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiencyJONES DARREN M·Filed 2010·Granted Apr 3, 2012·7 cites·16 claims
- 1577US5648733AScan compatible 3-state bus controlLSI LOGIC CORP·Filed 1995·Granted Jul 15, 1997·35 cites·6 claims
- 1674US8392663B2Coherent instruction cache utilizing cache-op execution resourcesKINTER RYAN C·Filed 2008·Granted Mar 5, 2013·7 cites·20 claims
- 1774US7917699B2Apparatus and method for controlling the exclusivity mode of a level-two cacheMIPS TECH INC·Filed 2007·Granted Mar 29, 2011·5 cites·23 claims
- 1874US7594089B2Smart memory based synchronization controller for a multi-threaded multiprocessor SoCMIPS TECH INC·Filed 2004·Granted Sep 22, 2009·20 cites·69 claims
- 1971US7237090B1Configurable out-of-order data transfer in a coprocessor interfaceMIPS TECH INC·Filed 2000·Granted Jun 26, 2007·17 cites·15 claims
- 2069US7315937B2Microprocessor instructions for efficient bit stream extractionsMIPS TECH INC·Filed 2004·Granted Jan 1, 2008·17 cites·39 claims
- 2167US7886129B2Configurable co-processor interfaceMIPS TECH INC·Filed 2004·Granted Feb 8, 2011·8 cites·10 claims
- 2266US7698533B2Configurable co-processor interfaceMIPS TECH INC·Filed 2007·Granted Apr 13, 2010·2 cites·27 claims
- 2358US6233656B1Bandwidth optimization cacheLSI LOGIC CORP·Filed 1997·Granted May 15, 2001·35 cites·7 claims
- 2454US7873810B2Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashionMIPS TECH INC·Filed 2004·Granted Jan 18, 2011·3 cites·25 claims
- 2550US8234456B2Apparatus and method for controlling the exclusivity mode of a level-two cacheKIM JINWOO·Filed 2011·Granted Jul 31, 2012·0 cites·23 claims
- 2637US6163540ASystem and method for establishing unique sequence identification in an information exchange of a system networkLSI LOGIC CORP·Filed 1998·Granted Dec 19, 2000·12 cites·12 claims
- 2735US6092167ARobust interface for high speed memory accessLSI LOGIC CORP·Filed 1998·Granted Jul 18, 2000·10 cites·10 claims
- 2835US6006283ASystem and method for managing information exchanges in a disk interface chipLSI LOGIC CORP·Filed 1998·Granted Dec 21, 1999·14 cites·12 claims
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