Inventor · disambiguated record
James H. Scheuneman
Also filed as: SCHEUNEMAN JAMES H · SCHEUNEMAN JAMES HERMAN
26 granted patents·1,240 citations·filing 1976–1990
97Inventor score
Top patents by PatentIndex Score
26 records- 0198US4112502AConditional bypass of error correction for dual memory access time selectionSPERRY RAND CORP·Filed 1977·Granted Sep 5, 1978·192 cites·3 claims
- 0296US4058851AConditional bypass of error correction for dual memory access time selectionSPERRY RAND CORP·Filed 1976·Granted Nov 15, 1977·119 cites·5 claims
- 0394US5060145AMemory access system for pipelined data paths to and from storageUNISYS CORP·Filed 1989·Granted Oct 22, 1991·89 cites·17 claims
- 0492US4633434AHigh performance storage unitSPERRY CORP·Filed 1984·Granted Dec 30, 1986·121 cites·5 claims
- 0591US4600986APipelined split stack with high performance interleaved decodeSPERRY CORP·Filed 1984·Granted Jul 15, 1986·108 cites·13 claims
- 0687US4996688AFault capture/fault injection systemUNISYS CORP·Filed 1988·Granted Feb 26, 1991·64 cites·4 claims
- 0782US4531213AMemory through checking system with comparison of data word parity before and after ECC processingSPERRY CORP·Filed 1984·Granted Jul 23, 1985·60 cites·4 claims
- 0879US4139148ADouble bit error correction using single bit error correction, double bit error detection logic and syndrome bit memorySPERRY RAND CORP·Filed 1977·Granted Feb 13, 1979·41 cites·5 claims
- 0978US4357686AHidden memory refreshSPERRY CORP·Filed 1980·Granted Nov 2, 1982·26 cites·2 claims
- 1077US4757440APipelined data stack with access through-checkingUNISYS CORP·Filed 1984·Granted Jul 12, 1988·48 cites·11 claims
- 1177US4070706AParallel requestor priority determination and requestor address matching in a cache memory systemSPERRY RAND CORP·Filed 1976·Granted Jan 24, 1978·37 cites·3 claims
- 1275US4652993AMultiple output port memory storage moduleSPERRY CORP·Filed 1984·Granted Mar 24, 1987·47 cites·2 claims
- 1375US4092713APost-write address word correction in cache memory systemSPERRY RAND CORP·Filed 1977·Granted May 30, 1978·35 cites·4 claims
- 1467US4953131AUnconditional clock and automatic refresh logicUNISYS CORP·Filed 1988·Granted Aug 28, 1990·26 cites·15 claims
- 1566US4163147ADouble bit error correction using double bit complementingSPERRY RAND CORP·Filed 1978·Granted Jul 31, 1979·26 cites·4 claims
- 1665US4649475AMultiple port memory with port decode error detectorSPERRY CORP·Filed 1984·Granted Mar 10, 1987·28 cites·14 claims
- 1763US4292674AOne word buffer memory systemSPERRY CORP·Filed 1979·Granted Sep 29, 1981·23 cites·18 claims
- 1862US4926426AError correction check during write cyclesUNISYS CORP·Filed 1988·Granted May 15, 1990·32 cites·2 claims
- 1960US4697233APartial duplication of pipelined stack with data integrity checkingUNISYS CORP·Filed 1984·Granted Sep 29, 1987·26 cites·9 claims
- 2054US4962501ABus data transmission verification systemUNISYS CORP·Filed 1988·Granted Oct 9, 1990·20 cites·6 claims
- 2147US4727510ASystem for addressing a multibank memory systemUNISYS CORP·Filed 1985·Granted Feb 23, 1988·16 cites·11 claims
- 2246US4918695AFailure detection for partial write operations for memoriesUNISYS CORP·Filed 1988·Granted Apr 17, 1990·17 cites·16 claims
- 2345US5068782AAccessing control with predetermined priority based on a feedback arrangementUNISYS CORP·Filed 1989·Granted Nov 26, 1991·14 cites·18 claims
- 2442US4918696ABank initiate error detectionUNISYS CORP·Filed 1988·Granted Apr 17, 1990·11 cites·2 claims
- 2535US4722052AMultiple unit adapterSPERRY CORP·Filed 1987·Granted Jan 26, 1988·6 cites·8 claims
- 2632US4989210APipelined address check bit stack controllerUNISYS CORP·Filed 1990·Granted Jan 29, 1991·8 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →