Inventor · disambiguated record
Sen-Fu Chen
Also filed as: CHEN SEN F · CHEN SEN-FU
19 granted patents·412 citations·filing 1996–2002
96Inventor score
Files withTAIWAN SEMICONDUCTOR MFG19
Top patents by PatentIndex Score
19 records- 0182US6001538ADamage free passivation layer etching processTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Dec 14, 1999·72 cites·12 claims
- 0279US6627971B1Polysilicon structures with different resistance values for gate electrodes, resistors, and capacitor platesTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Sep 30, 2003·21 cites·21 claims
- 0375US6682659B1Method for forming corrosion inhibited conductor layerTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jan 27, 2004·57 cites·16 claims
- 0470US6071826AMethod of manufacturing CMOS image sensor leakage free with double layer spacerTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jun 6, 2000·38 cites·37 claims
- 0569US6380030B1Implant method for forming Si3N4 spacerTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Apr 30, 2002·25 cites·15 claims
- 0665US6093629AMethod of simplified contact etching and ion implantation for CMOS technologyTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jul 25, 2000·24 cites·15 claims
- 0759US5639342AMethod of monitoring and controlling a silicon nitride etch stepTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted Jun 17, 1997·26 cites·22 claims
- 0859US5633210AMethod for forming damage free patterned layers adjoining the edges of high step height aperturesTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted May 27, 1997·27 cites·23 claims
- 0958US6624466B2Implant method for forming Si3N4 spacerTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Sep 23, 2003·7 cites·3 claims
- 1058US6394104B1Method of controlling and improving SOG etchback etcherTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted May 28, 2002·23 cites·12 claims
- 1152US5904570AMethod for polymer removal after etchingTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted May 18, 1999·17 cites·7 claims
- 1248US6162584AMethod of fabricating polysilicon structures with different resistance values for gate electrodes, resistors and capacitor plates in an integrated circuitTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Dec 19, 2000·14 cites·6 claims
- 1347US5719087AProcess for bonding pad protection from damageTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted Feb 17, 1998·15 cites·5 claims
- 1444US6211031B1Method to produce dual polysilicon resistance in an integrated circuitTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Apr 3, 2001·11 cites·22 claims
- 1541US6232172B1Method to prevent auto-doping induced threshold voltage shiftTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted May 15, 2001·7 cites·20 claims
- 1640US6077776APolysilicon residue free process by thermal treatmentTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jun 20, 2000·9 cites·19 claims
- 1739US6143474AMethod of fabricating polysilicon structures with different resistance values for gate electrodes, resistors, and capacitor platesTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Nov 7, 2000·7 cites·19 claims
- 1836US5763316ASubstrate isolation process to minimize junction leakageTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Jun 9, 1998·6 cites·13 claims
- 1934US6320269B1Method for preparing a semiconductor wafer to receive a protective tapeTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Nov 20, 2001·6 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →