Inventor · disambiguated record
Hiro Kinoshita
Also filed as: KINOSHITA HIRO
13 granted patents·1 pending application·75 citations·filing 2007–2016
89Inventor score
Files withSPANSION LLC5CHENG NING3SANDISK TECHNOLOGIES LLC2CYPRESS SEMICONDUCTOR CORP1FUJITSU TEN LTD1
Top patents by PatentIndex Score
14 records- 0196US9985046B2Method of forming a staircase in a semiconductor device using a linear alignment control featureSANDISK TECHNOLOGIES LLC·Filed 2016·Granted May 29, 2018·17 cites·9 claims
- 0295US10121794B2Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereofSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Nov 6, 2018·33 cites·18 claims
- 0390US9716101B2Forming 3D memory cells after word line replacementSANDISK TECHNOLOGIES INC·Filed 2015·Granted Jul 25, 2017·8 cites·11 claims
- 0483US8653581B2HTO offset for long Leffective, better device performanceCHENG NING·Filed 2008·Granted Feb 18, 2014·7 cites·20 claims
- 0582US9455352B2HTO offset for long leffective, better device performanceCYPRESS SEMICONDUCTOR CORP·Filed 2013·Granted Sep 27, 2016·4 cites·19 claims
- 0668US9224475B2Structures and methods for making NAND flash memorySEL JONGSUN·Filed 2012·Granted Dec 29, 2015·3 cites·8 claims
- 0763US7943983B2HTO offset spacers and dip off process to define junctionSPANSION LLC·Filed 2008·Granted May 17, 2011·3 cites·20 claims
- 0852US7935596B2HTO offset and BL trench process for memory device to improve device performanceSPANSION LLC·Filed 2008·Granted May 3, 2011·0 cites·20 claims
- 0950US8012830B2ORO and ORPRO with bit line trench to suppress transport program disturbSPANSION LLC·Filed 2007·Granted Sep 6, 2011·0 cites·9 claims
- 1050US7776688B2Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristicsSPANSION LLC·Filed 2007·Granted Aug 17, 2010·0 cites·20 claims
- 1149US2010208076A1Image recording condition setting apparatus, image recording condition setting method, and drive recorderFUJITSU TEN LTD·Filed 2008·Application pending·0 cites
- 1247US8330209B2HTO offset and BL trench process for memory device to improve device performanceCHENG NING·Filed 2011·Granted Dec 11, 2012·0 cites·20 claims
- 1347US7906807B2Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristicsSPANSION LLC·Filed 2010·Granted Mar 15, 2011·0 cites·20 claims
- 1445US9245895B2Oro and orpro with bit line trench to suppress transport program disturbCHENG NING·Filed 2011·Granted Jan 26, 2016·0 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →