Inventor · disambiguated record
John E. Barwin
Also filed as: BARWIN III JOHN E · BARWIN JOHN E
7 granted patents·4 pending applications·30 citations·filing 2004–2023
82Inventor score
Top patents by PatentIndex Score
11 records- 0177US7403061B2Method of improving fuse state detection and yield in semiconductor applicationsIBM·Filed 2006·Granted Jul 22, 2008·7 cites·16 claims
- 0276US8560990B2Method of managing electro migration in logic designs and design structure thereofBARWIN JOHN E·Filed 2010·Granted Oct 15, 2013·5 cites·2 claims
- 0375US8656325B2Integrated circuit design method and systemBARWIN JOHN E·Filed 2012·Granted Feb 18, 2014·5 cites·14 claims
- 0471US9104832B1Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip designIBM·Filed 2014·Granted Aug 11, 2015·3 cites·20 claims
- 0569US8938701B2Method of managing electro migration in logic designs and design structure thereofIBM·Filed 2013·Granted Jan 20, 2015·2 cites·13 claims
- 0661US7492199B2Fully synchronous DLL with architected update windowIBM·Filed 2006·Granted Feb 17, 2009·4 cites·2 claims
- 0749US2008265982A1Method of improving fuse state detection and yield in semiconductor applicationsIBM·Filed 2008·Application pending·0 cites
- 0848US2011107291A1Design system and method that, during timing analysis, compensates for regional timing variationsIBM·Filed 2009·Application pending·0 cites
- 0945US7057924B2Precharging the write path of an MRAM device for fast write operationIBM·Filed 2004·Granted Jun 6, 2006·4 cites·16 claims
- 1044US2009153228A1Structure for improving fuse state detection and yield in semiconductor applicationsIBM·Filed 2007·Application pending·0 cites
- 1143US2025328715A1Modeling mandrel tolerance in a design of a semiconductor deviceSYNOPSYS INC·Filed 2023·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →