Inventor · disambiguated record
Jon Allan Faue
Also filed as: FAUE JON · FAUE JON A · FAUE JON ALLAN
38 granted patents·3 pending applications·449 citations·filing 1994–2014
98Inventor score
Files withPROMOS TECHNOLOGIES INC15UNITED MEMORIES INC9MOSEL VITELIC INC7PROMOS TECHNOLOGIES PTE LTD7FAUE JON1
Top patents by PatentIndex Score
41 records- 0192US7061823B2Limited output address register technique providing selectively variable write latency in DDR2 (double data rate two) integrated circuit memory devicesPROMOS TECHNOLOGIES INC·Filed 2004·Granted Jun 13, 2006·76 cites·23 claims
- 0290US6415374B1System and method for supporting sequential burst counts in double data rate (DDR) synchronous dynamic random access memories (SDRAM)MOSEL VITELIC INC·Filed 2000·Granted Jul 2, 2002·57 cites·17 claims
- 0388US6337830B1Integrated clocking latency and multiplexer control technique for double data rate (DDR) synchronous dynamic random access memory (SDRAM) device data pathsMOSEL VITELIC INC·Filed 2000·Granted Jan 8, 2002·48 cites·24 claims
- 0485US5900021APad input select circuit for use with bond optionsUNITED MEMORIES INC·Filed 1997·Granted May 4, 1999·52 cites·18 claims
- 0578US7889579B2Using differential data strobes in non-differential mode to enhance data capture windowPROMOS TECHNOLOGIES PTE LTD·Filed 2008·Granted Feb 15, 2011·11 cites·10 claims
- 0674US6563747B2Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devicesMOSEL VITELIC INC·Filed 2001·Granted May 13, 2003·16 cites·6 claims
- 0773US6584578B1Arbitration method and circuit for control of integrated circuit double data rate (DDR) memory device output first-in, first-out (FIFO) registersMOSEL VITELIC INC·Filed 2000·Granted Jun 24, 2003·19 cites·21 claims
- 0867US7349289B2Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAMPROMOS TECHNOLOGIES INC·Filed 2005·Granted Mar 25, 2008·5 cites·20 claims
- 0966US6768367B1Pre-biased voltage level shifting circuit for integrated circuit devices utilizing differing power supply levelsPROMOS TECHNOLOGIES INC·Filed 2003·Granted Jul 27, 2004·16 cites·26 claims
- 1065US6359487B1System and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay lineMOSEL VITELIC INC·Filed 2000·Granted Mar 19, 2002·14 cites·21 claims
- 1163US7440351B2Wide window clock scheme for loading output FIFO registersPROMOS TECHNOLOGIES PTE LTD·Filed 2005·Granted Oct 21, 2008·2 cites·19 claims
- 1263US5438287AHigh speed differential current sense amplifier with positive feedbackUNITED MEMORIES INC·Filed 1994·Granted Aug 1, 1995·23 cites·13 claims
- 1362US9350338B2Linear progression delay registerUNITED MEMORIES INC·Filed 2014·Granted May 24, 2016·2 cites·20 claims
- 1462US6621747B2Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devicesMOSEL VITELIC INC·Filed 2002·Granted Sep 16, 2003·9 cites·16 claims
- 1561US7764565B2Multi-bank block architecture for integrated circuit memory devices having non-shared sense amplifier bands between banksPROMOS TECHNOLOGIES PTE LTD·Filed 2008·Granted Jul 27, 2010·4 cites·19 claims
- 1660US6741488B1Multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output assignments in an integrated circuit memory devicePROMOS TECHNOLOGIES INC·Filed 2002·Granted May 25, 2004·10 cites·22 claims
- 1758US7251172B2Efficient register for additive latency in DDR2 mode of operationPROMOS TECHNOLOGIES INC·Filed 2005·Granted Jul 31, 2007·5 cites·15 claims
- 1857US7039822B2Integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output sectionPROMOS TECHNOLOGIES INC·Filed 2003·Granted May 2, 2006·10 cites·28 claims
- 1956US6903592B2Limited variable width internal clock generationPROMOS TECHNOLOGIES INC·Filed 2003·Granted Jun 7, 2005·4 cites·18 claims
- 2054US7102439B2Low voltage differential amplifier circuit and a sampled low power bias control technique enabling accommodation of an increased range of input levelsPROMOS TECHNOLOGIES INC·Filed 2004·Granted Sep 5, 2006·7 cites·10 claims
- 2153US7830734B2Asymetric data path position and delays technique enabling high speed access in integrated circuit memory devicesPROMOS TECHNOLOGIES PTE LTD·Filed 2008·Granted Nov 9, 2010·2 cites·8 claims
- 2251US7167052B2Low voltage differential amplifier circuit for wide voltage range operationPROMOS TECHNOLOGIES INC·Filed 2004·Granted Jan 23, 2007·6 cites·21 claims
- 2351US7016235B2Data sorting in memoriesPROMOS TECHNOLOGIES PTE LTD·Filed 2004·Granted Mar 21, 2006·7 cites·30 claims
- 2451US6788589B2Programmable latch circuit inserted into write data path of an integrated circuit memoryPROMOS TECHNOLOGIES INC·Filed 2003·Granted Sep 7, 2004·6 cites·19 claims
- 2551US2008291748A1Wide window clock scheme for loading output fifo registersPROMOS TECHNOLOGIES PTE LTD·Filed 2008·Application pending·0 cites
- 2651US2008285371A1Wide window clock scheme for loading output fifo registersPROMOS TECHNOLOGIES PTE LTD·Filed 2008·Application pending·0 cites
- 2748US7298669B2Tri-mode clock generator to control memory array accessPROMOS TECHNOLOGIES INC·Filed 2006·Granted Nov 20, 2007·1 cites·8 claims
- 2848US6741520B1Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devicesMOSEL VITELIC INC·Filed 2000·Granted May 25, 2004·4 cites·14 claims
- 2946US8594114B2Shielding of datalines with physical placement based on time staggered accessFAUE JON·Filed 2008·Granted Nov 26, 2013·2 cites·17 claims
- 3045US9246475B2Dual-complementary integrating duty cycle detector with dead band noise rejectionUNITED MEMORIES INC·Filed 2014·Granted Jan 26, 2016·0 cites·24 claims
- 3145US5973980AFast voltage regulation without overshootUNITED MEMORIES INC·Filed 1998·Granted Oct 26, 1999·8 cites·5 claims
- 3243US9252759B1Linear progression delay registerUNITED MEMORIES INC·Filed 2014·Granted Feb 2, 2016·0 cites·23 claims
- 3343US7218564B2Dual equalization devices for long data line pairsPROMOS TECHNOLOGIES INC·Filed 2004·Granted May 15, 2007·3 cites·20 claims
- 3440US6128236ACurrent sensing differential amplifier with high rejection of power supply variations and method for an integrated circuit memory deviceNIPPON STEEL SEMICONDUCTOR·Filed 1998·Granted Oct 3, 2000·8 cites·15 claims
- 3540US2008137462A1Two-bit per i/o line write data bus for ddr1 and ddr2 operating modes in a dramPROMOS TECHNOLOGIES INC·Filed 2008·Application pending·0 cites
- 3639US5818291AFast voltage regulation without overshootUNITED MEMORIES INC·Filed 1997·Granted Oct 6, 1998·5 cites·13 claims
- 3736US7224637B2Tri-mode clock generator to control memory array accessPROMOS TECHNOLOGIES INC·Filed 2004·Granted May 29, 2007·0 cites·9 claims
- 3836US7091746B2Reduced device count level shifter with power savingsPROMOS TECHNOLOGIES INC·Filed 2004·Granted Aug 15, 2006·0 cites·24 claims
- 3933US6008688AApparatus, and associated method, for preventing occurrence of latch-up in an electronic circuitUNITED MEMORIES INC·Filed 1998·Granted Dec 28, 1999·2 cites·18 claims
- 4031US6285216B1High speed output enable path and method for an integrated circuit deviceUNITED MICROELECTRONICS CORP·Filed 1998·Granted Sep 4, 2001·3 cites·28 claims
- 4131US6201413B1Synchronous integrated circuit device utilizing an integrated clock/command techniqueUNITED MEMORIES INC·Filed 1998·Granted Mar 13, 2001·2 cites·23 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →