Inventor · disambiguated record
Peter Lee
Also filed as: LEE PETER · LEE PETER M · LEE PETER MAURICE
6 granted patents·3 pending applications·46 citations·filing 1996–2010
82Inventor score
Top patents by PatentIndex Score
9 records- 0179US7123049B2Output buffer circuit with control circuit for modifying supply voltage and transistor sizeRENESAS TECH CORP·Filed 2005·Granted Oct 17, 2006·8 cites·15 claims
- 0268US6937059B2Output buffer circuit with control circuit for modifying supply voltage and transistor sizeRENESAS TECH CORP·Filed 2003·Granted Aug 30, 2005·11 cites·15 claims
- 0367US6634015B2Computer-readable storage media stored with a delay library for designing a semiconductor integrated circuit deviceHITACHI LTD·Filed 2001·Granted Oct 14, 2003·13 cites·13 claims
- 0463US6952112B2Output buffer circuit with control circuit for modifying supply voltage and transistor sizeRENESAS TECH CORP·Filed 2000·Granted Oct 4, 2005·8 cites·16 claims
- 0562US7721234B2Simulation method and simulation programRENESAS TECH CORP·Filed 2007·Granted May 18, 2010·2 cites·4 claims
- 0645US2010199239A1Simulation method and simulation programRENESAS TECH CORP·Filed 2010·Application pending·0 cites
- 0741US2001032329A1Storage media being readable by a computer, and a method for designing a semiconductor integrated circuit deviceHITACHI LTD·Filed 2001·Application pending·0 cites
- 0840US2007219770A1Simulation methodLEE PETER M·Filed 2006·Application pending·0 cites
- 0931US5742071AWiringless logical operation circuitsHITACHI LTD·Filed 1996·Granted Apr 21, 1998·4 cites·21 claims
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