Inventor · disambiguated record
Peter Ramyalal Suaris
Also filed as: SUARIS PETER · SUARIS PETER R · SUARIS PETER RAMYALAL
7 granted patents·4 pending applications·196 citations·filing 1998–2024
86Inventor score
Files withMADURAWE RAMINDA UDAYA2SUARIS PETER RAMYALAL2WAVE COMPUTING INC2ADHIKARI A A KAVINDU RAVISHKA1MENTOR GRAPHICS CORP1
Top patents by PatentIndex Score
11 records- 0197US7673273B2MPGA products based on a prototype FPGATIER LOGIC INC·Filed 2007·Granted Mar 2, 2010·115 cites·20 claims
- 0285USRE45110EMPGA products based on a prototype FPGAMADURAWE RAMINDA UDAYA·Filed 2012·Granted Sep 2, 2014·6 cites·31 claims
- 0382US7203919B2Retiming circuits using a cut-based approachSUARIS PETER·Filed 2004·Granted Apr 10, 2007·49 cites·46 claims
- 0465US2025356194A1Genetic algorithm-based adaptive batch selection for hessian quantization in neural networksADHIKARI A A KAVINDU RAVISHKA·Filed 2024·Application pending·0 cites
- 0562US7716622B2Memory re-implementation for field programmable gate arraysSUARIS PETER RAMYALAL·Filed 2007·Granted May 11, 2010·4 cites·24 claims
- 0657US10042966B2Computing resource allocation based on flow graph translationWAVE SEMICONDUCTOR INC·Filed 2015·Granted Aug 7, 2018·1 cites·26 claims
- 0750US7251803B2Memory re-implementation for field programmable gate arraysSUARIS PETER RAMYALAL·Filed 2004·Granted Jul 31, 2007·5 cites·13 claims
- 0843US6223334B1Automatic topology synthesis and optimizationMENTOR GRAPHICS CORP·Filed 1998·Granted Apr 24, 2001·16 cites·13 claims
- 0936US2008024165A1Configurable embedded multi-port memoryMADURAWE RAMINDA UDAYA·Filed 2006·Application pending·0 cites
- 1036US2018341734A1Reconfigurable computing resource allocation using flow graph translationWAVE COMPUTING INC·Filed 2018·Application pending·0 cites
- 1135US2019042941A1Reconfigurable fabric operation linkageWAVE COMPUTING INC·Filed 2018·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →