Inventor · disambiguated record
Hongzhou Liu
Also filed as: LIU HONGZHOU
29 granted patents·219 citations·filing 2003–2021
96Inventor score
Top patents by PatentIndex Score
29 records- 0195US10853550B1Sampling selection for enhanced high yield estimation in circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Dec 1, 2020·11 cites·18 claims
- 0295US9836564B1Efficient extraction of the worst sample in Monte Carlo simulationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Dec 5, 2017·17 cites·20 claims
- 0395US9805158B1Efficient extraction of K-sigma corners from Monte Carlo simulationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 31, 2017·17 cites·20 claims
- 0493US11416660B1Automatic placement of analog design components with virtual groupingCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Aug 16, 2022·5 cites·20 claims
- 0593US9524365B1Efficient monte carlo flow via failure probability modelingCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Dec 20, 2016·21 cites·20 claims
- 0692US10528644B1Estimation and visualization of a full probability distribution for circuit performance obtained with Monte Carlo simulations over scaled sigma samplingCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jan 7, 2020·9 cites·20 claims
- 0789US8954910B1Device mismatch contribution computation with nonlinear effectsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Feb 10, 2015·13 cites·17 claims
- 0889US8954908B1Fast monte carlo statistical analysis using threshold voltage modelingCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Feb 10, 2015·17 cites·21 claims
- 0986US10776548B1Parallel Monte Carlo sampling for predicting tail performance of integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Sep 15, 2020·5 cites·20 claims
- 1086US7493574B2Method and system for improving yield of an integrated circuitCADENCE DESIGNS SYSTEMS INC·Filed 2006·Granted Feb 17, 2009·19 cites·27 claims
- 1185US8813009B1Computing device mismatch variation contributionsCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Aug 19, 2014·8 cites·20 claims
- 1283US10325056B1Failure boundary classification and corner creation for scaled-sigma samplingCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jun 18, 2019·4 cites·20 claims
- 1381US10084476B1Adaptive lossless compression in analog mixed signal environmentsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Sep 25, 2018·7 cites·20 claims
- 1481US8589852B1Statistical corner extraction using worst-case distanceLIU HONGZHOU·Filed 2011·Granted Nov 19, 2013·7 cites·27 claims
- 1579US10909293B1Sampling selection for enhanced high yield estimation in circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Feb 2, 2021·1 cites·20 claims
- 1679US8479126B1Parametric yield improvement flow incorporating sigma to target distanceLIU HONGZHOU·Filed 2007·Granted Jul 2, 2013·11 cites·22 claims
- 1777US8219355B2Methods and systems for high sigma yield estimationTIWARY SAURABH·Filed 2009·Granted Jul 10, 2012·11 cites·21 claims
- 1876US11562110B1System and method for device mismatch contribution computation for non-continuous circuit outputsCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jan 24, 2023·2 cites·20 claims
- 1972US10114916B1Method and system to accelerate visualization of waveform dataCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 30, 2018·4 cites·21 claims
- 2070US12045730B1System, method, and computer program product for analog and mix-signal circuit placementCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jul 23, 2024·1 cites·16 claims
- 2168US7533358B2Integrated sizing, layout, and extractor tool for circuit designCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted May 12, 2009·4 cites·21 claims
- 2268US6957400B2Method and apparatus for quantifying tradeoffs for multiple competing goals in circuit designCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Oct 18, 2005·15 cites·39 claims
- 2366US10262092B1Interactive platform to predict mismatch variation and contribution when adjusting component parametersCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Apr 16, 2019·1 cites·20 claims
- 2465US7712055B2Designing integrated circuits for yieldCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted May 4, 2010·4 cites·21 claims
- 2560US8195427B2Methods and systems for high sigma yield estimation using reduced dimensionalityTIWARY SAURABH·Filed 2009·Granted Jun 5, 2012·4 cites·28 claims
- 2658US7346868B2Method and system for evaluating design costs of an integrated circuitCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Mar 18, 2008·1 cites·36 claims
- 2751US11790147B1System and method for routing in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Oct 17, 2023·0 cites·18 claims
- 2843US10289764B1Parallel extraction of worst case cornersCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted May 14, 2019·0 cites·20 claims
- 2937US10275555B1Yield estimation for a post-layout circuit designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Apr 30, 2019·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →