Inventor · disambiguated record
Robert A. Alfieri
Also filed as: ALFIERI ROBERT · ALFIERI ROBERT A · ALFIERI ROBERT ANTHONY
53 granted patents·9 pending applications·1,515 citations·filing 1994–2025
98Inventor score
Top patents by PatentIndex Score
62 records- 0198US5745778AApparatus and method for improved CPU affinity in a multiprocessor systemDATA GENERAL CORP·Filed 1994·Granted Apr 28, 1998·551 cites·32 claims
- 0293US8928681B1Coalescing to avoid read-modify-write during compressed data operationsEDMONDSON JOHN H·Filed 2009·Granted Jan 6, 2015·13 cites·15 claims
- 0393US7363610B2Building integrated circuits using a common databaseNVIDIA CORP·Filed 2005·Granted Apr 22, 2008·37 cites·20 claims
- 0493US7324547B1Internet protocol (IP) router residing in a processor chipsetNVIDIA CORP·Filed 2002·Granted Jan 29, 2008·87 cites·28 claims
- 0593US6105053AOperating system for a non-uniform memory access multiprocessor systemEMC CORP·Filed 1995·Granted Aug 15, 2000·332 cites·29 claims
- 0691US7496788B1Watchdog monitoring for unit status reportingNVIDIA CORP·Filed 2006·Granted Feb 24, 2009·28 cites·20 claims
- 0790US7397797B2Method and apparatus for performing network processing functionsNVIDIA CORP·Filed 2002·Granted Jul 8, 2008·60 cites·31 claims
- 0888US9058792B1Coalescing to avoid read-modify-write during compressed data operationsEDMONDSON JOHN H·Filed 2006·Granted Jun 16, 2015·8 cites·14 claims
- 0988US7483823B2Building integrated circuits using logical unitsNVIDIA CORP·Filed 2005·Granted Jan 27, 2009·19 cites·24 claims
- 1084US8429661B1Managing multi-threaded FIFO memory by determining whether issued credit count for dedicated class of threads is less than limitALFIERI ROBERT A·Filed 2005·Granted Apr 23, 2013·21 cites·18 claims
- 1184US7120653B2Method and apparatus for providing an integrated file systemNVIDIA CORP·Filed 2002·Granted Oct 10, 2006·41 cites·44 claims
- 1283US11663773B2Using importance resampling to reduce the memory incoherence of light samplingNVIDIA CORP·Filed 2021·Granted May 30, 2023·1 cites·23 claims
- 1382US8930861B2System, method, and computer program product for constructing a data flow and identifying a constructNVIDIA CORP·Filed 2013·Granted Jan 6, 2015·5 cites·19 claims
- 1482US7383352B2Method and apparatus for providing an integrated network of processorsNVIDIA CORP·Filed 2006·Granted Jun 3, 2008·7 cites·25 claims
- 1581US7188250B1Method and apparatus for performing network processing functionsNVIDIA CORP·Filed 2002·Granted Mar 6, 2007·34 cites·18 claims
- 1681US5666486AMultiprocessor cluster membership manager frameworkDATA GENERAL CORP·Filed 1995·Granted Sep 9, 1997·148 cites·44 claims
- 1781US2025259377A1Using importance resampling to reduce the memory incoherence of light samplingNVIDIA CORP·Filed 2025·Application pending·0 cites
- 1880US12361633B2Using importance resampling to reduce the memory incoherence of light samplingNVIDIA CORP·Filed 2023·Granted Jul 15, 2025·0 cites·20 claims
- 1980US9015646B2System, method, and computer program product for translating a hardware language into a source databaseNVIDIA CORP·Filed 2013·Granted Apr 21, 2015·5 cites·20 claims
- 2080US7630389B1Multi-thread FIFO memory generatorNVIDIA CORP·Filed 2006·Granted Dec 8, 2009·11 cites·20 claims
- 2179US7685371B1Hierarchical flush barrier mechanism with deadlock avoidanceNVIDIA CORP·Filed 2006·Granted Mar 23, 2010·9 cites·11 claims
- 2278US7362772B1Network processing pipeline chipset for routing and host packet processingNVIDIA CORP·Filed 2002·Granted Apr 22, 2008·23 cites·37 claims
- 2376US9244810B2Debugger graphical user interface system, method, and computer program productNVIDIA CORP·Filed 2013·Granted Jan 26, 2016·4 cites·21 claims
- 2476US7437548B1Network level protocol negotiation and operationNVIDIA CORP·Filed 2002·Granted Oct 14, 2008·22 cites·16 claims
- 2574US12159344B2Accelerated processing via a physically based rendering engineNVIDIA CORP·Filed 2023·Granted Dec 3, 2024·0 cites·28 claims
- 2674US9171115B2System, method, and computer program product for translating a common hardware database into a logic code modelNVIDIA CORP·Filed 2013·Granted Oct 27, 2015·3 cites·20 claims
- 2774US8943448B2System, method, and computer program product for providing a debugger using a common hardware databaseNVIDIA CORP·Filed 2013·Granted Jan 27, 2015·3 cites·21 claims
- 2873US8094670B1Method and apparatus for performing network processing functionsALFIERI ROBERT A·Filed 2007·Granted Jan 10, 2012·5 cites·19 claims
- 2971US7631152B1Determining memory flush states for selective heterogeneous memory flushesNVIDIA CORP·Filed 2006·Granted Dec 8, 2009·5 cites·19 claims
- 3070US9021408B2System, method, and computer program product for translating a source database into a common hardware databaseNVIDIA CORP·Filed 2013·Granted Apr 28, 2015·2 cites·20 claims
- 3170US9015643B2System, method, and computer program product for applying a callback function to data valuesNVIDIA CORP·Filed 2013·Granted Apr 21, 2015·2 cites·19 claims
- 3267US11704860B2Accelerated processing via a physically based rendering engineNVIDIA CORP·Filed 2021·Granted Jul 18, 2023·0 cites·20 claims
- 3364US9189199B2Folded FIFO memory generatorNVIDIA CORP·Filed 2012·Granted Nov 17, 2015·1 cites·22 claims
- 3463US11875444B2Accelerated processing via a physically based rendering engineNVIDIA CORP·Filed 2021·Granted Jan 16, 2024·0 cites·24 claims
- 3561US9281817B2Power conservation using gray-coded address sequencingNVIDIA CORP·Filed 2012·Granted Mar 8, 2016·2 cites·20 claims
- 3661US9106401B2Deterministic synchronization for transmitting signals between different clock domainsALFIERI ROBERT A·Filed 2012·Granted Aug 11, 2015·1 cites·23 claims
- 3760US11908064B2Accelerated processing via a physically based rendering engineNVIDIA CORP·Filed 2021·Granted Feb 20, 2024·0 cites·19 claims
- 3860US7961178B1Method and system for reordering isochronous hub streamsNVIDIA CORP·Filed 2007·Granted Jun 14, 2011·2 cites·20 claims
- 3958US11853764B2Accelerated processing via a physically based rendering engineNVIDIA CORP·Filed 2021·Granted Dec 26, 2023·0 cites·20 claims
- 4058US11830123B2Accelerated processing via a physically based rendering engineNVIDIA CORP·Filed 2021·Granted Nov 28, 2023·0 cites·19 claims
- 4158US8201172B1Multi-threaded FIFO memory with speculative read and write capabilityOLIVEIRA MARCIO T·Filed 2007·Granted Jun 12, 2012·3 cites·19 claims
- 4258US6920484B2Method and apparatus for providing an integrated virtual disk subsystemNVIDIA CORP·Filed 2002·Granted Jul 19, 2005·5 cites·91 claims
- 4357US8051126B2Method and apparatus for providing an integrated network of processorsNVIDIA CORP·Filed 2009·Granted Nov 1, 2011·0 cites·19 claims
- 4456US7756148B1Multi-threaded FIFO memory generator with speculative read and write capabilityNVIDIA CORP·Filed 2007·Granted Jul 13, 2010·1 cites·20 claims
- 4555US8963940B1Isochronous hub contractsRIACH DUNCAN A·Filed 2007·Granted Feb 24, 2015·0 cites·20 claims
- 4654US7961733B2Method and apparatus for performing network processing functionsNVIDIA CORP·Filed 2008·Granted Jun 14, 2011·0 cites·23 claims
- 4754US7620738B2Method and apparatus for providing an integrated network of processorsNVIDIA CORP·Filed 2007·Granted Nov 17, 2009·0 cites·7 claims
- 4852US7924868B1Internet protocol (IP) router residing in a processor chipsetNVIDIA CORP·Filed 2007·Granted Apr 12, 2011·0 cites·14 claims
- 4952US2014278328A1System, method, and computer program product for constructing a data flow and identifying a constructNVIDIA CORP·Filed 2013·Application pending·0 cites
- 5050US8789006B2System, method, and computer program product for testing an integrated circuit from a command lineNVIDIA CORP·Filed 2012·Granted Jul 22, 2014·0 cites·20 claims
Showing the top 50 of 62 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Robert A. Alfieri files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →