Inventor · disambiguated record
Yasukazu Mase
Also filed as: MASE YASUKAZU
19 granted patents·618 citations·filing 1984–1998
96Inventor score
Top patents by PatentIndex Score
19 records- 0193US5655954APolishing apparatusTOSHIBA MACHINE CO LTD·Filed 1995·Granted Aug 12, 1997·161 cites·21 claims
- 0279US5055906ASemiconductor device having a composite insulating interlayerTOSHIBA KK·Filed 1991·Granted Oct 8, 1991·67 cites·19 claims
- 0378US4634496AMethod for planarizing the surface of an interlayer insulating film in a semiconductor deviceTOSHIBA KK·Filed 1985·Granted Jan 6, 1987·52 cites·5 claims
- 0473US5044311APlasma chemical vapor deposition apparatusTOSHIBA KK·Filed 1989·Granted Sep 3, 1991·27 cites·14 claims
- 0573US5016663AMethod of determining end of cleaning of semiconductor manufacturing apparatusTOSHIBA KK·Filed 1988·Granted May 21, 1991·39 cites·2 claims
- 0672US5169407AMethod of determining end of cleaning of semiconductor manufacturing apparatusTOSHIBA KK·Filed 1990·Granted Dec 8, 1992·50 cites·2 claims
- 0772US5100476AMethod and apparatus for cleaning semiconductor devicesTOSHIBA KK·Filed 1990·Granted Mar 31, 1992·49 cites·20 claims
- 0870US4613888ASemiconductor device of multilayer wiring structureTOSHIBA KK·Filed 1984·Granted Sep 23, 1986·30 cites·16 claims
- 0963US5258328AMethod of forming multilayered wiring structure of semiconductor deviceTOSHIBA KK·Filed 1993·Granted Nov 2, 1993·33 cites·16 claims
- 1059US4952528APhotolithographic method for manufacturing semiconductor wiring patternsTOSHIBA KK·Filed 1989·Granted Aug 28, 1990·19 cites·7 claims
- 1155US4857141AMethod of forming holes in semiconductor integrated circuit deviceTOSHIBA KK·Filed 1988·Granted Aug 15, 1989·20 cites·12 claims
- 1254US4728627AMethod of making multilayered interconnects using hillock studs formed by sinteringTOSHIBA KK·Filed 1986·Granted Mar 1, 1988·15 cites·13 claims
- 1350US6015754AChemical mechanical polishing apparatus and methodTOSHIBA KK·Filed 1997·Granted Jan 18, 2000·16 cites·20 claims
- 1442US5126819AWiring pattern of semiconductor integrated circuit deviceTOSHIBA KK·Filed 1990·Granted Jun 30, 1992·9 cites·3 claims
- 1541US5103287AMulti-layered wiring structure of semiconductor integrated circuit deviceTOSHIBA KK·Filed 1990·Granted Apr 7, 1992·12 cites·13 claims
- 1640US5523627AWiring pattern of semiconductor integrated circuit deviceTOSHIBA KK·Filed 1995·Granted Jun 4, 1996·7 cites·5 claims
- 1739US5175115AMethod of controlling metal thin film formation conditionsTOSHIBA KK·Filed 1991·Granted Dec 29, 1992·10 cites·10 claims
- 1830US5411916AMethod for patterning wirings of semiconductor integrated circuit deviceTOSHIBA KK·Filed 1993·Granted May 2, 1995·2 cites·20 claims
- 1929USRE37059EWiring pattern of semiconductor integrated circuit deviceTOSHIBA KK·Filed 1998·Granted Feb 20, 2001·0 cites·31 claims
Join the waitlist — get patent alerts
Get an alert when Yasukazu Mase files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →