Inventor · disambiguated record
David Alan Koeplinger
Also filed as: KOEPLINGER DAVID ALAN
16 granted patents·8 pending applications·68 citations·filing 2019–2025
91Inventor score
Files withSAMBANOVA SYSTEMS INC24
Top patents by PatentIndex Score
24 records- 0196US11709664B2Anti-congestion flow control for reconfigurable processorsSAMBANOVA SYSTEMS INC·Filed 2020·Granted Jul 25, 2023·11 cites·31 claims
- 0296US11237971B1Compile time logic for detecting streaming compatible and broadcast compatible data access patternsSAMBANOVA SYSTEMS INC·Filed 2020·Granted Feb 1, 2022·13 cites·20 claims
- 0396US11080227B2Compiler flow logic for reconfigurable architecturesSAMBANOVA SYSTEMS INC·Filed 2019·Granted Aug 3, 2021·22 cites·25 claims
- 0495US11645057B2Systems and methods for memory layout determination and conflict resolutionSAMBANOVA SYSTEMS INC·Filed 2020·Granted May 9, 2023·6 cites·21 claims
- 0592US11782729B2Runtime patching of configuration filesSAMBANOVA SYSTEMS INC·Filed 2020·Granted Oct 10, 2023·3 cites·18 claims
- 0690US11714780B2Compiler flow logic for reconfigurable architecturesSAMBANOVA SYSTEMS INC·Filed 2021·Granted Aug 1, 2023·2 cites·23 claims
- 0790US10768899B2Matrix normal/transpose read and a reconfigurable data processor including sameSAMBANOVA SYSTEMS INC·Filed 2019·Granted Sep 8, 2020·9 cites·25 claims
- 0887US12254300B2Merging buffer access operations in a coarse-grained reconfigurable computing systemSAMBANOVA SYSTEMS INC·Filed 2022·Granted Mar 18, 2025·1 cites·25 claims
- 0986US12164463B2Buffer splittingSAMBANOVA SYSTEMS INC·Filed 2023·Granted Dec 10, 2024·1 cites·19 claims
- 1079US2025306883A1Compiler-based synchronization for dataflow graphs on coarse-grained reconfigurable architecturesSAMBANOVA SYSTEMS INC·Filed 2025·Application pending·0 cites
- 1177US2025328328A1Operation Fusion in Reconfigurable Dataflow ProcessorsSAMBANOVA SYSTEMS INC·Filed 2025·Application pending·0 cites
- 1276US12236220B2Flow control for reconfigurable processorsSAMBANOVA SYSTEMS INC·Filed 2023·Granted Feb 25, 2025·0 cites·18 claims
- 1373US12333283B2Iterative compilation to optimize translation in reconfigurable dataflow architecturesSAMBANOVA SYSTEMS INC·Filed 2023·Granted Jun 17, 2025·0 cites·20 claims
- 1473US12260199B2Merging skip-buffers in a reconfigurable dataflow processorSAMBANOVA SYSTEMS INC·Filed 2023·Granted Mar 25, 2025·0 cites·19 claims
- 1573US2025190192A1Flow control for reconfigurable processors using control countersSAMBANOVA SYSTEMS INC·Filed 2025·Application pending·0 cites
- 1672US2025199788A1Merging Skip- BuffersSAMBANOVA SYSTEMS INC·Filed 2025·Application pending·0 cites
- 1772US2025068587A1Buffer Splitting Based on CostSAMBANOVA SYSTEMS INC·Filed 2024·Application pending·0 cites
- 1870US12373182B2Compiler-based input synchronization for processor with variant stage latenciesSAMBANOVA SYSTEMS INC·Filed 2022·Granted Jul 29, 2025·0 cites·20 claims
- 1970US2023409233A1Buffer Fusion and Layout OptimizationSAMBANOVA SYSTEMS INC·Filed 2022·Application pending·0 cites
- 2070US2025231748A1Merging Buffer Access Operations of a Compute GraphSAMBANOVA SYSTEMS INC·Filed 2025·Application pending·0 cites
- 2169US12386602B2Operation fusion in nested meta-pipeline loopsSAMBANOVA SYSTEMS INC·Filed 2023·Granted Aug 12, 2025·0 cites·20 claims
- 2268US2023376292A1Compile time logic for detecting and resolving memory layout conflictsSAMBANOVA SYSTEMS INC·Filed 2023·Application pending·0 cites
- 2364US12105630B2Compile time logic for inserting a buffer between a producer operation unit and a consumer operation unit in a dataflow graphSAMBANOVA SYSTEMS INC·Filed 2022·Granted Oct 1, 2024·0 cites·22 claims
- 2459US12430109B2Critical stage optimization for reconfigurable architecturesSAMBANOVA SYSTEMS INC·Filed 2023·Granted Sep 30, 2025·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →