Inventor · disambiguated record
Kun-Han Tsai
Also filed as: TSAI KUN-HAN
16 granted patents·1 pending application·118 citations·filing 2004–2019
92Inventor score
Top patents by PatentIndex Score
17 records- 0193US7555689B2Generating responses to patterns stimulating an electronic circuit with timing exception pathsGOSWAMI DHIRAJ·Filed 2006·Granted Jun 30, 2009·27 cites·40 claims
- 0289US9086454B2Timing-aware test generation and fault simulationMENTOR GRAPHICS CORP·Filed 2013·Granted Jul 21, 2015·8 cites·13 claims
- 0387US7239978B2Compactor independent fault diagnosisCHENG WU-TUNG·Filed 2004·Granted Jul 3, 2007·45 cites·46 claims
- 0483US8051352B2Timing-aware test generation and fault simulationMENTOR GRAPHICS CORP·Filed 2007·Granted Nov 1, 2011·9 cites·24 claims
- 0583US7984354B2Generating responses to patterns stimulating an electronic circuit with timing exception pathsMENTOR GRAPHICS CORP·Filed 2009·Granted Jul 19, 2011·10 cites·21 claims
- 0681US9720040B2Timing-aware test generation and fault simulationMENTOR GRAPHICS CORP·Filed 2015·Granted Aug 1, 2017·2 cites·17 claims
- 0780US11361248B2Multi-stage machine learning-based chain diagnosisSIEMENS IND SOFTWARE INC·Filed 2019·Granted Jun 14, 2022·5 cites·20 claims
- 0879US8527232B2Diagnostic test pattern generation for small delay defectGUO RUIFENG·Filed 2010·Granted Sep 3, 2013·4 cites·12 claims
- 0973US8301414B2Compactor independent fault diagnosisCHENG WU-TUNG·Filed 2007·Granted Oct 30, 2012·5 cites·29 claims
- 1071US11681843B2Input data compression for machine learning-based chain diagnosisSIEMENS IND SOFTWARE INC·Filed 2019·Granted Jun 20, 2023·1 cites·21 claims
- 1171US10317462B2Wide-range clock signal generation for speed grading of logic coresMENTOR GRAPHICS CORP·Filed 2017·Granted Jun 11, 2019·1 cites·14 claims
- 1266US8560906B2Timing-aware test generation and fault simulationLIN XIJIANG·Filed 2011·Granted Oct 15, 2013·1 cites·17 claims
- 1359US10977400B2Deterministic test pattern generation for designs with timing exceptionsMENTOR GRAPHICS CORP·Filed 2019·Granted Apr 13, 2021·0 cites·20 claims
- 1459US10509073B2Timing-aware test generation and fault simulationLIN XIJIANG·Filed 2017·Granted Dec 17, 2019·0 cites·11 claims
- 1552US9720038B2Method and circuit of pulse-vanishing testMENTOR GRAPHICS CORP·Filed 2014·Granted Aug 1, 2017·0 cites·10 claims
- 1644US8468409B2Speed-path debug using at-speed scan test patternsGUO RUIFENG·Filed 2009·Granted Jun 18, 2013·0 cites·33 claims
- 1744US2014246705A1Programmable Leakage Test For Interconnects In Stacked DesignsMENTOR GRAPHICS CORP·Filed 2014·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →