Inventor · disambiguated record
Jesus Corbal San Adrian
Also filed as: SAN ADRIAN JESUS CORBAL
14 granted patents·7 pending applications·24 citations·filing 2011–2024
87Inventor score
Top patents by PatentIndex Score
21 records- 0193US11113053B2Data element comparison processors, methods, systems, and instructionsINTEL CORP·Filed 2019·Granted Sep 7, 2021·8 cites·20 claims
- 0292US9513917B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2014·Granted Dec 6, 2016·10 cites·14 claims
- 0388US2024427600A1Vector friendly instruction format and execution thereofINTEL CORP·Filed 2024·Application pending·0 cites
- 0484US12086594B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2023·Granted Sep 10, 2024·0 cites·23 claims
- 0576US11740904B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2021·Granted Aug 29, 2023·0 cites·20 claims
- 0675US9552205B2Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and instructionsINTEL CORP·Filed 2013·Granted Jan 24, 2017·3 cites·25 claims
- 0773US11210096B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2020·Granted Dec 28, 2021·0 cites·28 claims
- 0872US10445092B2Method and apparatus for performing a vector permute with an index and an immediateINTEL CORP·Filed 2014·Granted Oct 15, 2019·3 cites·21 claims
- 0966US10795680B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2019·Granted Oct 6, 2020·0 cites·9 claims
- 1058US9785437B2Method and apparatus for performing a vector bit reversal and crossingINTEL CORP·Filed 2014·Granted Oct 10, 2017·0 cites·25 claims
- 1157US2020097290A1Method and apparatus for performing a vector permute with an index and an immediateINTEL CORP·Filed 2019·Application pending·0 cites
- 1254US2015052333A1Systems, Apparatuses, and Methods for Stride Pattern Gathering of Data Elements and Stride Pattern Scattering of Data ElementsHUGHES CHRISTOPHER J·Filed 2014·Application pending·0 cites
- 1352US10423411B2Data element comparison processors, methods, systems, and instructionsINTEL CORP·Filed 2015·Granted Sep 24, 2019·0 cites·23 claims
- 1451US2013305020A1Vector friendly instruction format and execution thereofVALENTINE ROBERT C·Filed 2011·Application pending·0 cites
- 1550US10296489B2Method and apparatus for performing a vector bit shuffleINTEL CORP·Filed 2014·Granted May 21, 2019·0 cites·25 claims
- 1650US10296334B2Method and apparatus for performing a vector bit gatherINTEL CORP·Filed 2014·Granted May 21, 2019·0 cites·25 claims
- 1748US10255072B2Architectural register replacement for instructions that use multiple architectural registersINTEL CORP·Filed 2016·Granted Apr 9, 2019·0 cites·23 claims
- 1847US2016188333A1Method and apparatus for compressing a mask valueINTEL CORP·Filed 2014·Application pending·0 cites
- 1945US9696992B2Apparatus and method for performing a check to optimize instruction flowINTEL CORP·Filed 2014·Granted Jul 4, 2017·0 cites·25 claims
- 2041US2012254593A1Systems, apparatuses, and methods for jumps using a mask registerSAN ADRIAN JESUS CORBAL·Filed 2011·Application pending·0 cites
- 2139US2012254592A1Systems, apparatuses, and methods for expanding a memory source into a destination register and compressing a source register into a destination memory locationSAN ADRIAN JESUS CORBAL·Filed 2011·Application pending·0 cites
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