Inventor · disambiguated record
Stephen A. Neuendorffer
Also filed as: NEUENDORFFER STEPHEN A · NEUENDORFFER STEPHEN ANDREW
22 granted patents·175 citations·filing 2006–2021
95Inventor score
Top patents by PatentIndex Score
22 records- 0196US8359448B1Specific memory controller implemented using reconfigurationXILINX INC·Filed 2009·Granted Jan 22, 2013·61 cites·20 claims
- 0290US11422781B1Generation of vector codes for tensor convolutionsXILINX INC·Filed 2020·Granted Aug 23, 2022·6 cites·20 claims
- 0388US10031732B1Operation processing for high level synthesisXILINX INC·Filed 2016·Granted Jul 24, 2018·6 cites·15 claims
- 0488US9824172B1Performance of circuitry generated using high-level synthesisXILINX INC·Filed 2016·Granted Nov 21, 2017·8 cites·20 claims
- 0587US9710584B1Performance of circuitry generated using high-level synthesisXILINX INC·Filed 2016·Granted Jul 18, 2017·7 cites·20 claims
- 0687US7765512B1Relocatable circuit implemented in a programmable logic deviceXILINX INC·Filed 2008·Granted Jul 27, 2010·16 cites·12 claims
- 0786US7541833B1Validating partial reconfiguration of an integrated circuitXILINX INC·Filed 2007·Granted Jun 2, 2009·15 cites·20 claims
- 0883US10671779B1Function calls in high level synthesisXILINX INC·Filed 2018·Granted Jun 2, 2020·3 cites·20 claims
- 0977US9081930B1Throughput during high level synthesisXILINX INC·Filed 2014·Granted Jul 14, 2015·6 cites·19 claims
- 1075US9449131B2Extracting system architecture in high level synthesisXILINX INC·Filed 2014·Granted Sep 20, 2016·5 cites·17 claims
- 1174US8219960B1Methods of implementing relocatable circuits in a programmable integrated circuit deviceNEUENDORFFER STEPHEN A·Filed 2010·Granted Jul 10, 2012·4 cites·19 claims
- 1273US7895026B1Multi-rate simulation scheduler for synchronous digital circuits in a high level modeling systemXILINX INC·Filed 2007·Granted Feb 22, 2011·6 cites·20 claims
- 1371US7653762B1Profiling circuit arrangementXILINX INC·Filed 2007·Granted Jan 26, 2010·9 cites·16 claims
- 1469US8122239B1Method and apparatus for initializing a system configured in a programmable logic deviceJAMES-ROXBY PHILIP B·Filed 2008·Granted Feb 21, 2012·6 cites·20 claims
- 1567US8116334B1Dataflow FIFO communication buffer using highly-multiported memoriesNEUENDORFFER STEPHEN A·Filed 2010·Granted Feb 14, 2012·2 cites·12 claims
- 1666US8020139B1Method and apparatus for implementing a dataflow circuit model using application-specific memory implementationsXILINX INC·Filed 2008·Granted Sep 13, 2011·3 cites·20 claims
- 1765US8245243B1Transforming device drivers to improve efficiencyNEUENDORFFER STEPHEN A·Filed 2009·Granted Aug 14, 2012·3 cites·20 claims
- 1865US7525343B1Method and apparatus for accessing internal registers of hardware blocks in a programmable logic deviceXILINX INC·Filed 2007·Granted Apr 28, 2009·4 cites·20 claims
- 1963US7969187B1Hardware interface in an integrated circuitXILINX INC·Filed 2010·Granted Jun 28, 2011·1 cites·17 claims
- 2063US7869452B1Dataflow FIFO communication buffer using highly-multiported memoriesXILINX INC·Filed 2007·Granted Jan 11, 2011·2 cites·10 claims
- 2163US7834658B1Interface generation for coupling to a high-bandwidth interfaceXILINX INC·Filed 2006·Granted Nov 16, 2010·2 cites·12 claims
- 2251US11651127B2Placement of logic based on relative activation ratesXILINX INC·Filed 2021·Granted May 16, 2023·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →