Inventor · disambiguated record
Kai Weber
Also filed as: WEBER KAI · WEBER KAI O · WEBER KAI OLIVER
24 granted patents·4 pending applications·120 citations·filing 2004–2019
94Inventor score
Technology areasG06F
Top patents by PatentIndex Score
28 records- 0191US9594683B2Data processing in a multiple processor system to maintain multiple processor cache memory access coherencyIBM·Filed 2014·Granted Mar 14, 2017·35 cites·12 claims
- 0285US7290229B2Method and system for optimized handling of constraints during symbolic simulationIBM·Filed 2005·Granted Oct 30, 2007·16 cites·20 claims
- 0379US7302656B2Method and system for performing functional verification of logic circuitsIBM·Filed 2006·Granted Nov 27, 2007·13 cites·12 claims
- 0475US7890903B2Method and system for formal verification of an electronic circuit designIBM·Filed 2008·Granted Feb 15, 2011·8 cites·10 claims
- 0571US8249848B2Verifying a processor design using a processor simulation modelLETZ STEFAN·Filed 2008·Granted Aug 21, 2012·6 cites·15 claims
- 0670US8600724B2Verifying a processor design using a processor simulation modelLETZ STEFAN·Filed 2012·Granted Dec 3, 2013·3 cites·20 claims
- 0770US7340473B2Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuitIBM·Filed 2004·Granted Mar 4, 2008·12 cites·8 claims
- 0870US7340704B2Method and system for optimized automated case-splitting via constraints in a symbolic simulation frameworkIBM·Filed 2005·Granted Mar 4, 2008·4 cites·7 claims
- 0968US7865793B2Test case generation with backward propagation of predefined results and operand dependenciesIBM·Filed 2008·Granted Jan 4, 2011·5 cites·1 claims
- 1066US7752583B2System for verification of digital designs using case-splitting via constrained internal signalsIBM·Filed 2007·Granted Jul 6, 2010·2 cites·6 claims
- 1166US7506290B2Method and system for case-splitting on nodes in a symbolic simulation frameworkIBM·Filed 2007·Granted Mar 17, 2009·2 cites·8 claims
- 1265US9329863B2Load register on condition with zero or immediate instructionIBM·Filed 2013·Granted May 3, 2016·1 cites·9 claims
- 1365US7624363B2Method and apparatus for performing equivalence checking on circuit designs having differing clocking and latching schemesIBM·Filed 2007·Granted Nov 24, 2009·3 cites·5 claims
- 1465US7363603B2Method and system for case-splitting on nodes in a symbolic simulation frameworkIBM·Filed 2005·Granted Apr 22, 2008·2 cites·8 claims
- 1564US7367001B2Method, system and computer program product for verification of digital designs using case-splitting via constrained internal signalsIBM·Filed 2004·Granted Apr 29, 2008·7 cites·6 claims
- 1663US11010160B2Load register on condition immediate instructionIBM·Filed 2019·Granted May 18, 2021·0 cites·20 claims
- 1755US10235168B2Load register on condition immediate or immediate instructionIBM·Filed 2016·Granted Mar 19, 2019·0 cites·15 claims
- 1853US7853917B2System for building binary decision diagrams efficiently in a structural network representation of a digital circuitIBM·Filed 2007·Granted Dec 14, 2010·0 cites·8 claims
- 1953US7475371B2Method and system for case-splitting on nodes in a symbolic simulation frameworkIBM·Filed 2007·Granted Jan 6, 2009·0 cites·7 claims
- 2053US7458048B2Computer program product for verification of digital designs using case-splitting via constrained internal signalsIBM·Filed 2007·Granted Nov 25, 2008·0 cites·5 claims
- 2152US8402403B2Verifying a register-transfer level design of an execution unitLETZ STEFAN·Filed 2010·Granted Mar 19, 2013·1 cites·15 claims
- 2252US7836413B2Building binary decision diagrams efficiently in a structural network representation of a digital circuitIBM·Filed 2007·Granted Nov 16, 2010·0 cites·8 claims
- 2351US2008092096A1Method and system for optimized automated case-splitting via constraints in a symbolic simulation frameworkBAUMGARTNER JASON R·Filed 2007·Application pending·0 cites
- 2447US7949968B2Method and system for building binary decision diagrams optimally for nodes in a netlist graph using don't-caringIBM·Filed 2007·Granted May 24, 2011·0 cites·14 claims
- 2542US2007050435A1Leading-Zero Counter and Method to Count Leading ZerosJACOBI CHRISTIAN·Filed 2006·Application pending·0 cites
- 2642US2007050740A1Method and System for Performing Functional Formal Verification of Logic CircuitsJACOBI CHRISTIAN·Filed 2006·Application pending·0 cites
- 2740US2013096901A1Verifying Simulation Design ModificationsGELLERICH WOLFGANG·Filed 2011·Application pending·0 cites
- 2837US9218442B2Firmware and hardware verification using Opcode comparisonKRYGOWSKI CHRISTOPHER A·Filed 2010·Granted Dec 22, 2015·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →