Inventor · disambiguated record
Vivek Trivedi
Also filed as: TRIVEDI VIVEK
14 granted patents·1 pending application·62 citations·filing 2003–2023
89Inventor score
Top patents by PatentIndex Score
15 records- 0196US11150687B1Low-latency retimer with seamless clock switchoverASTERA LABS INC·Filed 2020·Granted Oct 19, 2021·7 cites·21 claims
- 0294US11487317B1Low-latency retimer with seamless clock switchoverASTERA LABS INC·Filed 2021·Granted Nov 1, 2022·3 cites·21 claims
- 0390US11258696B1Low-latency signaling-link retimerASTERA LABS INC·Filed 2020·Granted Feb 22, 2022·3 cites·18 claims
- 0488US8683416B1Integrated circuit optimizationTRIVEDI VIVEK·Filed 2011·Granted Mar 25, 2014·27 cites·21 claims
- 0578US12277002B1Low-latency retimer with seamless clock switchoverASTERA LABS INC·Filed 2023·Granted Apr 15, 2025·0 cites·21 claims
- 0678US9443053B2System for and method of placing clock stations using variable drive-strength clock drivers built out of a smaller subset of base cells for hybrid tree-mesh clock distribution networksXPLIANT INC·Filed 2013·Granted Sep 13, 2016·7 cites·23 claims
- 0774US11853115B1Low-latency retimer with seamless clock switchoverASTERA LABS INC·Filed 2022·Granted Dec 26, 2023·0 cites·18 claims
- 0862US7299433B2Timing analysis apparatus, systems, and methodsINTEL CORP·Filed 2003·Granted Nov 20, 2007·15 cites·27 claims
- 0961US12143288B1Low-latency signaling-link retimerASTERA LABS INC·Filed 2022·Granted Nov 12, 2024·0 cites·21 claims
- 1054US11327913B1Configurable-aggregation retimer with media-dedicated controllersASTERA LABS INC·Filed 2020·Granted May 10, 2022·0 cites·22 claims
- 1152US9098664B2Integrated circuit optimizationJUNIPER NETWORKS INC·Filed 2014·Granted Aug 4, 2015·0 cites·20 claims
- 1245US10198389B2Baseboard interconnection device, system and methodCAVIUM INC·Filed 2014·Granted Feb 5, 2019·0 cites·25 claims
- 1344US9390209B2System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networksXPLIANT INC·Filed 2013·Granted Jul 12, 2016·0 cites·22 claims
- 1444US2016014885A1Network device, system and method having a rotated chip floorplanXPLIANT INC·Filed 2014·Application pending·0 cites
- 1542US9305129B2System for and method of tuning clock networks constructed using variable drive-strength clock inverters with variable drive-strength clock drivers built out of a smaller subset of base cellsXPLIANT INC·Filed 2013·Granted Apr 5, 2016·0 cites·30 claims
Join the waitlist — get patent alerts
Get an alert when Vivek Trivedi files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →