Inventor · disambiguated record
Xijiang Lin
Also filed as: LIN XIJIANG
20 granted patents·127 citations·filing 1999–2020
94Inventor score
Top patents by PatentIndex Score
20 records- 0196US7925465B2Low power scan testing techniques and apparatusMENTOR GRAPHICS CORP·Filed 2008·Granted Apr 12, 2011·37 cites·48 claims
- 0293US8290738B2Low power scan testing techniques and apparatusLIN XIJIANG·Filed 2011·Granted Oct 16, 2012·12 cites·31 claims
- 0392US7865792B2Test generation methods for reducing power dissipation and supply currentsMENTOR GRAPHICS CORP·Filed 2010·Granted Jan 4, 2011·10 cites·31 claims
- 0491US8499209B2At-speed scan testing with controlled switching activityRAJSKI JANUSZ·Filed 2010·Granted Jul 30, 2013·12 cites·23 claims
- 0589US9086454B2Timing-aware test generation and fault simulationMENTOR GRAPHICS CORP·Filed 2013·Granted Jul 21, 2015·8 cites·13 claims
- 0687US11635462B2Library cell modeling for transistor-level test pattern generationMENTOR GRAPHICS CORP·Filed 2020·Granted Apr 25, 2023·2 cites·17 claims
- 0784US7685491B2Test generation methods for reducing power dissipation and supply currentsLIN XIJIANG·Filed 2007·Granted Mar 23, 2010·11 cites·27 claims
- 0883US8051352B2Timing-aware test generation and fault simulationMENTOR GRAPHICS CORP·Filed 2007·Granted Nov 1, 2011·9 cites·24 claims
- 0981US9720040B2Timing-aware test generation and fault simulationMENTOR GRAPHICS CORP·Filed 2015·Granted Aug 1, 2017·2 cites·17 claims
- 1079US8890563B2Scan cell use with reduced power consumptionLIN XIJIANG·Filed 2009·Granted Nov 18, 2014·9 cites·14 claims
- 1178US9568552B2Logic built-in self-test with high test coverage and low switching activityMENTOR GRAPHICS CORP·Filed 2014·Granted Feb 14, 2017·3 cites·17 claims
- 1274US9501589B2Identification of power sensitive scan cellsMENTOR GRAPHICS CORP·Filed 2014·Granted Nov 22, 2016·3 cites·8 claims
- 1366US10372855B2Scan cell selection for partial scan designsMENTOR GRAPHICS CORP·Filed 2015·Granted Aug 6, 2019·1 cites·14 claims
- 1466US8560906B2Timing-aware test generation and fault simulationLIN XIJIANG·Filed 2011·Granted Oct 15, 2013·1 cites·17 claims
- 1564US8996941B2Test data volume reduction based on test cube propertiesMENTOR GRAPHICS CORP·Filed 2013·Granted Mar 31, 2015·1 cites·10 claims
- 1659US10977400B2Deterministic test pattern generation for designs with timing exceptionsMENTOR GRAPHICS CORP·Filed 2019·Granted Apr 13, 2021·0 cites·20 claims
- 1759US10509073B2Timing-aware test generation and fault simulationLIN XIJIANG·Filed 2017·Granted Dec 17, 2019·0 cites·11 claims
- 1852US9335374B2Dynamic shift for test pattern compressionMENTOR GRAPHICS CORP·Filed 2014·Granted May 10, 2016·0 cites·16 claims
- 1946US10222420B2Transition test generation for detecting cell internal defectsMENTOR GRAPHICS CORP·Filed 2017·Granted Mar 5, 2019·0 cites·19 claims
- 2035US6378096B1On-line partitioning for sequential circuit test generationNEC USA INC·Filed 1999·Granted Apr 23, 2002·6 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →