Inventor · disambiguated record
Marc Loinaz
Also filed as: LOINAZ MARC · LOINAZ MARC J · LOINAZ MARC JOSEPH
29 granted patents·625 citations·filing 1997–2022
97Inventor score
Files withLOINAZ MARC8NETLOGIC MICROSYSTEMS INC7AGERE SYST GUARDIAN CORP3AELUROS INC2NET LOGIC MICROSYSTEMS INC2
Top patents by PatentIndex Score
29 records- 0197US7323916B1Methods and apparatus for generating multiple clocks using feedback interpolationNETLOGIC MICROSYSTEMS INC·Filed 2005·Granted Jan 29, 2008·97 cites·14 claims
- 0296US7679345B1Digital linear voltage regulatorNETLOGIC MICROSYSTEMS INC·Filed 2007·Granted Mar 16, 2010·37 cites·12 claims
- 0396US7532697B1Methods and apparatus for clock and data recovery using a single sourceNET LOGIC MICROSYSTEMS INC·Filed 2005·Granted May 12, 2009·75 cites·14 claims
- 0496US7436229B2Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolationNET LOGIC MICROSYSTEMS INC·Filed 2007·Granted Oct 14, 2008·39 cites·20 claims
- 0594US7432750B1Methods and apparatus for frequency synthesis with feedback interpolationNETLOGIC MICROSYSTEMS INC·Filed 2005·Granted Oct 7, 2008·27 cites·18 claims
- 0693US6346907B1Analog-to-digital converter having voltage to-time converter and time digitizer, and method for using sameAGERE SYST GUARDIAN CORP·Filed 1999·Granted Feb 12, 2002·160 cites·18 claims
- 0791US8000412B1Low power serial linkNETLOGIC MICROSYSTEMS INC·Filed 2007·Granted Aug 16, 2011·20 cites·23 claims
- 0890US8618967B2Systems, circuits, and methods for a sigma-delta based time to digital converterNIKAEEN PARASTOO·Filed 2012·Granted Dec 31, 2013·15 cites·20 claims
- 0989US11480514B2Fluorescence lifetime imaging (FLIM) and flow cytometry applications for a time synchronized sensor networkLOINAZ MARC·Filed 2019·Granted Oct 25, 2022·3 cites·19 claims
- 1089US6377082B1Loss-of-signal detector for clock/data recovery circuitsAGERE SYST GUARDIAN CORP·Filed 2000·Granted Apr 23, 2002·65 cites·24 claims
- 1184US10911171B2High precision multi-chip clock synchronizationLOINAZ MARC·Filed 2019·Granted Feb 2, 2021·3 cites·17 claims
- 1284US8423814B2Programmable drive strength in memory signalingLOINAZ MARC·Filed 2010·Granted Apr 16, 2013·7 cites·26 claims
- 1378US6788103B1Activ shunt-peaked logic gatesAELUROS INC·Filed 2002·Granted Sep 7, 2004·17 cites·29 claims
- 1475US8552767B1Systems, circuits, and methods for a digital frequency synthesizerNIKAEEN PARASTOO·Filed 2012·Granted Oct 8, 2013·5 cites·24 claims
- 1575US8433018B2Methods and apparatus for frequency synthesis with feedback interpolationSIDIROPOULOS STEFANOS·Filed 2008·Granted Apr 30, 2013·6 cites·20 claims
- 1674US12021536B2Positron emission tomography system with a time synchronized networkLOINAZ MARC·Filed 2022·Granted Jun 25, 2024·0 cites·13 claims
- 1772US11619719B2Time coherent networkLOINAZ MARC·Filed 2019·Granted Apr 4, 2023·2 cites·16 claims
- 1871US7919957B2Digital linear voltage regulatorNETLOGIC MICROSYSTEMS INC·Filed 2010·Granted Apr 5, 2011·3 cites·19 claims
- 1963US8520744B2Multi-value logic signaling in multi-functional circuitsLOINAZ MARC·Filed 2010·Granted Aug 27, 2013·1 cites·20 claims
- 2062US6141050AMOS image sensorLUCENT TECHNOLOGIES INC·Filed 1997·Granted Oct 31, 2000·25 cites·33 claims
- 2157US12166570B2High precision multi-chip clock synchronizationANACAPA SEMICONDUCTOR INC·Filed 2020·Granted Dec 10, 2024·0 cites·14 claims
- 2257US12081223B2Lidar system with a time synchronized sensor network for precision sensingLOINAZ MARC·Filed 2019·Granted Sep 3, 2024·0 cites·9 claims
- 2357US7009425B1Methods and apparatus for improving large signal performance for active shunt-peaked circuitsAELUROS INC·Filed 2004·Granted Mar 7, 2006·6 cites·18 claims
- 2455US9094020B2Multi-value logic signaling in multi-functional circuitsNETLOGIC MICROSYSTEMS INC·Filed 2013·Granted Jul 28, 2015·0 cites·20 claims
- 2555US8700944B2Programmable drive strength in memory signalingNETLOGIC MICROSYSTEMS INC·Filed 2013·Granted Apr 15, 2014·0 cites·20 claims
- 2649US8964905B1Low power serial linkLOINAZ MARC·Filed 2011·Granted Feb 24, 2015·0 cites·23 claims
- 2749US8638896B2Repeate architecture with single clock multiplier unitLIU DEAN·Filed 2010·Granted Jan 28, 2014·1 cites·20 claims
- 2843US6417717B1Hierarchical multiplexer for analog array readoutAGERE SYST GUARDIAN CORP·Filed 1998·Granted Jul 9, 2002·7 cites·53 claims
- 2936US6677995B1Array readout systemAGERE SYSTEMS INC·Filed 1999·Granted Jan 13, 2004·4 cites·28 claims
Join the waitlist — get patent alerts
Get an alert when Marc Loinaz files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →