Inventor · disambiguated record
Balasubramanian S. Haran
Also filed as: HARAN BALASUBRAMANIAN · HARAN BALASUBRAMANIAN S · HARAN BALASUBRAMANIAN S PRANATHARTHI
84 granted patents·20 pending applications·790 citations·filing 2009–2016
99Inventor score
Top patents by PatentIndex Score
104 records- 0198US8569152B1Cut-very-last dual-epi flowBASKER VEERARAGHAVAN S·Filed 2012·Granted Oct 29, 2013·65 cites·20 claims
- 0298US8420459B1Bulk fin-field effect transistors with well defined isolationCHENG KANGGUO·Filed 2011·Granted Apr 16, 2013·67 cites·20 claims
- 0398US8358012B2Metal semiconductor alloy structure for low contact resistanceIBM·Filed 2010·Granted Jan 22, 2013·53 cites·19 claims
- 0497US8999774B2Bulk fin-field effect transistors with well defined isolationIBM·Filed 2013·Granted Apr 7, 2015·18 cites·15 claims
- 0597US8604539B2Bulk fin-field effect transistors with well defined isolationCHENG KANGGUO·Filed 2012·Granted Dec 10, 2013·18 cites·20 claims
- 0697US8581320B1MOS capacitors with a finfet processCHENG KANGGUO·Filed 2012·Granted Nov 12, 2013·28 cites·20 claims
- 0796US8987790B2Fin isolation in multi-gate field effect transistorsIBM·Filed 2012·Granted Mar 24, 2015·22 cites·15 claims
- 0896US8623712B2Bulk fin-field effect transistors with well defined isolationIBM·Filed 2013·Granted Jan 7, 2014·15 cites·20 claims
- 0996US8455932B2Local interconnect structure self-aligned to gate structureKHAKIFIROOZ ALI·Filed 2011·Granted Jun 4, 2013·28 cites·20 claims
- 1095US9406679B2Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gateIBM·Filed 2015·Granted Aug 2, 2016·10 cites·9 claims
- 1195US8932918B2FinFET with self-aligned punchthrough stopperCHENG KANGGUO·Filed 2012·Granted Jan 13, 2015·17 cites·20 claims
- 1295US8232607B2Borderless contact for replacement gate employing selective depositionEDGE LISA F·Filed 2010·Granted Jul 31, 2012·42 cites·20 claims
- 1394US9000522B2FinFET with dielectric isolation by silicon-on-nothing and method of fabricationIBM·Filed 2013·Granted Apr 7, 2015·13 cites·9 claims
- 1494US8928067B2Bulk fin-field effect transistors with well defined isolationIBM·Filed 2013·Granted Jan 6, 2015·10 cites·20 claims
- 1594US8592290B1Cut-very-last dual-EPI flowBASKER VEERARAGHAVAN S·Filed 2012·Granted Nov 26, 2013·16 cites·20 claims
- 1694US8394710B2Semiconductor devices fabricated by doped material layer as dopant sourceCHENG KANGGUO·Filed 2010·Granted Mar 12, 2013·15 cites·12 claims
- 1794US8383490B2Borderless contact for ultra-thin body devicesIBM·Filed 2011·Granted Feb 26, 2013·15 cites·10 claims
- 1894US8309447B2Method for integrating multiple threshold voltage devices for CMOSCHENG KANGGUO·Filed 2010·Granted Nov 13, 2012·21 cites·27 claims
- 1993US9269629B2Dummy fin formation by gas cluster ion beamGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 23, 2016·11 cites·8 claims
- 2093US9087921B2CMOS with dual raised source and drain for NMOS and PMOSIBM·Filed 2015·Granted Jul 21, 2015·7 cites·6 claims
- 2193US9087741B2CMOS with dual raised source and drain for NMOS and PMOSCHENG KANGGUO·Filed 2011·Granted Jul 21, 2015·11 cites·2 claims
- 2293US8946792B2Dummy fin formation by gas cluster ion beamIBM·Filed 2012·Granted Feb 3, 2015·12 cites·2 claims
- 2392US9263466B2CMOS with dual raised source and drain for NMOS and PMOSIBM·Filed 2015·Granted Feb 16, 2016·6 cites·11 claims
- 2492US8617961B1Post-gate isolation area formation for fin field effect transistor deviceHARAN BALASUBRAMANIAN S·Filed 2012·Granted Dec 31, 2013·14 cites·20 claims
- 2592US8486778B2Low resistance source and drain extensions for ETSOIHARAN BALASUBRAMANIAN S·Filed 2011·Granted Jul 16, 2013·13 cites·5 claims
- 2691US9406570B2FinFET deviceGlobalfoundries·Filed 2015·Granted Aug 2, 2016·6 cites·6 claims
- 2791US9299719B2CMOS with dual raised source and drain for NMOS and PMOSIBM·Filed 2015·Granted Mar 29, 2016·5 cites·8 claims
- 2890US8889564B2Suspended nanowire structureCHENG KANGGUO·Filed 2012·Granted Nov 18, 2014·8 cites·10 claims
- 2990US8435846B2Semiconductor devices with raised extensionsCHENG KANGGUO·Filed 2011·Granted May 7, 2013·9 cites·8 claims
- 3090US8432002B2Method and structure for low resistive source and drain regions in a replacement metal gate process flowHARAN BALASUBRAMANIAN S·Filed 2011·Granted Apr 30, 2013·11 cites·25 claims
- 3190US8377795B2Cut first methodology for double exposure double etch integrationIBM·Filed 2010·Granted Feb 19, 2013·11 cites·13 claims
- 3289US8859379B2Stress enhanced finFET devicesIBM·Filed 2013·Granted Oct 14, 2014·9 cites·12 claims
- 3389US8829617B2Uniform finFET gate heightIBM·Filed 2012·Granted Sep 9, 2014·9 cites·6 claims
- 3489US8673708B2Replacement gate ETSOI with sharp junctionCHENG KANGGUO·Filed 2012·Granted Mar 18, 2014·8 cites·10 claims
- 3589US8569125B2FinFET with improved gate planaritySTANDAERT THEODORUS EDUARDUS·Filed 2011·Granted Oct 29, 2013·12 cites·15 claims
- 3689US8440552B1Method to form low series resistance transistor devices on silicon on insulator layerCHEN KANGGUO·Filed 2012·Granted May 14, 2013·17 cites·18 claims
- 3788US8592263B2FinFET diode with increased junction areaSTANDAERT THEODORUS EDUARDUS·Filed 2012·Granted Nov 26, 2013·11 cites·11 claims
- 3887US9368590B2Silicon-on-insulator transistor with self-aligned borderless source/drain contactsGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 14, 2016·7 cites·6 claims
- 3987US9263465B2CMOS with dual raised source and drain for NMOS and PMOSIBM·Filed 2015·Granted Feb 16, 2016·3 cites·3 claims
- 4087US9219068B2FinFET with dielectric isolation by silicon-on-nothing and method of fabricationIBM·Filed 2014·Granted Dec 22, 2015·5 cites·7 claims
- 4184US10388729B2Devices and methods of forming self-aligned, uniform nano sheet spacersGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 20, 2019·4 cites·10 claims
- 4284US8796128B2Dual metal fill and dual threshold voltage for replacement gate metal devicesEDGE LISA F·Filed 2012·Granted Aug 5, 2014·9 cites·13 claims
- 4382US9082873B2Method and structure for finFET with finely controlled device widthIBM·Filed 2012·Granted Jul 14, 2015·6 cites·8 claims
- 4482US8987070B2SOI device with embedded liner in box layer to limit STI recessCHENG KANGGUO·Filed 2012·Granted Mar 24, 2015·5 cites·19 claims
- 4582US8673738B2Shallow trench isolation structuresDORIS BRUCE B·Filed 2012·Granted Mar 18, 2014·4 cites·14 claims
- 4682US8642415B2Semiconductor substrate with transistors having different threshold voltagesADAM THOMAS N·Filed 2012·Granted Feb 4, 2014·5 cites·9 claims
- 4782US8623730B2Method for fabricating silicon-on-insulator transistor with self-aligned borderless source/drain contactsFAN SUSAN S·Filed 2012·Granted Jan 7, 2014·7 cites·20 claims
- 4881US9478549B2FinFET with dielectric isolation by silicon-on-nothing and method of fabricationGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 25, 2016·3 cites·10 claims
- 4981US8790991B2Method and structure for shallow trench isolation to mitigate active shortsCUMMINGS JASON E·Filed 2011·Granted Jul 29, 2014·6 cites·10 claims
- 5081US8614486B2Low resistance source and drain extensions for ETSOIHARAN BALASUBRAMANIAN S·Filed 2012·Granted Dec 24, 2013·5 cites·10 claims
Showing the top 50 of 104 patent records by PatentIndex Score.
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