Inventor · disambiguated record
Brian J. Greene
Also filed as: GREENE BRIAN · GREENE BRIAN J · GREENE BRIAN JOSEPH
102 granted patents·19 pending applications·848 citations·filing 2004–2025
99Inventor score
Top patents by PatentIndex Score
121 records- 0198US9437496B1Merged source drain epitaxyGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 6, 2016·26 cites·20 claims
- 0298US8236661B2Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakageDENNARD ROBERT H·Filed 2009·Granted Aug 7, 2012·134 cites·6 claims
- 0398US7358551B2Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regionsIBM·Filed 2005·Granted Apr 15, 2008·76 cites·11 claims
- 0497US8476706B1CMOS having a SiC/SiGe alloy stackCHIDAMBARRAO DURESETI·Filed 2012·Granted Jul 2, 2013·29 cites·12 claims
- 0596US10074571B1Device with decreased pitch contact to active regionsGLOBALFOUNDRIES INC·Filed 2017·Granted Sep 11, 2018·17 cites·19 claims
- 0696US9312274B1Merged fin structures for finFET devicesIBM·Filed 2014·Granted Apr 12, 2016·27 cites·20 claims
- 0796US8354309B2Method of providing threshold voltage adjustment through gate dielectric stack modificationIBM·Filed 2012·Granted Jan 15, 2013·24 cites·20 claims
- 0895US10269932B1Asymmetric formation of epi semiconductor material in source/drain regions of FinFET devicesGLOBALFOUNDRIES INC·Filed 2018·Granted Apr 23, 2019·42 cites·17 claims
- 0995US7989298B1Transistor having V-shaped embedded stressorIBM·Filed 2010·Granted Aug 2, 2011·27 cites·20 claims
- 1095US7405131B2Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressorCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Jul 29, 2008·45 cites·26 claims
- 1194US7659157B2Dual metal gate finFETs with single or dual high-K gate dielectricIBM·Filed 2007·Granted Feb 9, 2010·29 cites·12 claims
- 1293US10083878B1Fin fabrication process with dual shallow trench isolation and tunable inner and outer fin profileGLOBALFOUNDRIES INC·Filed 2017·Granted Sep 25, 2018·9 cites·13 claims
- 1393US7132322B1Method for forming a SiGe or SiGeC gate selectively in a complementary MIS/MOS FET deviceIBM·Filed 2005·Granted Nov 7, 2006·27 cites·20 claims
- 1492US9171954B2FinFET structure and method to adjust threshold voltage in a FinFET structureIBM·Filed 2014·Granted Oct 27, 2015·9 cites·14 claims
- 1592US7939413B2Embedded stressor structure and processSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted May 10, 2011·27 cites·27 claims
- 1691US8853035B2Tucked active region without dummy poly for performance boost and variation reductionYU XIAOJUN·Filed 2011·Granted Oct 7, 2014·9 cites·12 claims
- 1791US7442618B2Method to engineer etch profiles in Si substrate for advanced semiconductor devicesCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Oct 28, 2008·22 cites·21 claims
- 1891US7002209B2MOSFET structure with high mechanical stress in the channelIBM·Filed 2004·Granted Feb 21, 2006·61 cites·20 claims
- 1989US8115254B2Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating sameZHU HUILONG·Filed 2007·Granted Feb 14, 2012·14 cites·15 claims
- 2089US7479437B2Method to reduce contact resistance on thin silicon-on-insulator deviceIBM·Filed 2006·Granted Jan 20, 2009·13 cites·17 claims
- 2187US9093275B2Multi-height multi-composition semiconductor finsIBM·Filed 2013·Granted Jul 28, 2015·6 cites·15 claims
- 2287US7365399B2Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing costIBM·Filed 2006·Granted Apr 29, 2008·12 cites·6 claims
- 2387US7205639B2Semiconductor devices with rotated substrates and methods of manufacture thereofIBM·Filed 2005·Granted Apr 17, 2007·12 cites·16 claims
- 2484US8772149B2FinFET structure and method to adjust threshold voltage in a FinFET structureCARTIER EDUARD A·Filed 2011·Granted Jul 8, 2014·5 cites·8 claims
- 2584US7977185B2Method and apparatus for post silicide spacer removalIBM·Filed 2005·Granted Jul 12, 2011·9 cites·14 claims
- 2684US7812397B2Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereofIBM·Filed 2008·Granted Oct 12, 2010·8 cites·20 claims
- 2784US7449378B2Structure and method for improved stress and yield in pFETS with embedded SiGe source/drain regionsIBM·Filed 2008·Granted Nov 11, 2008·9 cites·9 claims
- 2882US8633096B2Creating anisotropically diffused junctions in field effect transistor devicesGREENE BRIAN J·Filed 2010·Granted Jan 21, 2014·5 cites·13 claims
- 2982US8222673B2Self-aligned embedded SiGe structure and method of manufacturing the sameGREENE BRIAN J·Filed 2010·Granted Jul 17, 2012·5 cites·11 claims
- 3082US7843024B2Method and structure for improving device performance variation in dual stress liner technologyIBM·Filed 2008·Granted Nov 30, 2010·7 cites·28 claims
- 3181US12166031B2Substrate-less electrostatic discharge (ESD) integrated circuit structuresINTEL CORP·Filed 2020·Granted Dec 10, 2024·1 cites·20 claims
- 3281US8932949B2FinFET structure and method to adjust threshold voltage in a FinFET structureIBM·Filed 2014·Granted Jan 13, 2015·3 cites·17 claims
- 3381US7767541B2Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methodsIBM·Filed 2005·Granted Aug 3, 2010·6 cites·22 claims
- 3481US7538339B2Scalable strained FET device and method of fabricating the sameIBM·Filed 2006·Granted May 26, 2009·7 cites·5 claims
- 3580US8993389B2Dummy gate interconnect for semiconductor deviceIBM·Filed 2013·Granted Mar 31, 2015·5 cites·17 claims
- 3680US8598009B2Self-aligned embedded SiGe structure and method of manufacturing the sameGREENE BRIAN J·Filed 2012·Granted Dec 3, 2013·4 cites·20 claims
- 3778US8106455B2Threshold voltage adjustment through gate dielectric stack modificationGREENE BRIAN J·Filed 2009·Granted Jan 31, 2012·6 cites·19 claims
- 3878US7833873B2Method and structure to reduce contact resistance on thin silicon-on-insulator deviceIBM·Filed 2008·Granted Nov 16, 2010·5 cites·17 claims
- 3977US10991796B2Source/drain contact depth controlGLOBALFOUNDRIES US INC·Filed 2018·Granted Apr 27, 2021·2 cites·10 claims
- 4077US8941189B2Fin-shaped field effect transistor (finFET) structures having multiple threshold voltages (Vt) and method of formingIBM·Filed 2013·Granted Jan 27, 2015·4 cites·18 claims
- 4176US12471354B2Dipole threshold voltage tuning for high voltage transistor stacksINTEL CORP·Filed 2020·Granted Nov 11, 2025·1 cites·20 claims
- 4276US9991167B2Method and IC structure for increasing pitch between gatesGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 5, 2018·2 cites·18 claims
- 4376US9780002B1Threshold voltage and well implantation method for semiconductor devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 3, 2017·2 cites·20 claims
- 4476US7462522B2Method and structure for improving device performance variation in dual stress liner technologyIBM·Filed 2006·Granted Dec 9, 2008·5 cites·1 claims
- 4576US7449374B2Methods of manufacturing semiconductor devices with rotated substratesINFINEON TECHNOLOGIES AG·Filed 2007·Granted Nov 11, 2008·5 cites·24 claims
- 4674US9379185B2Method of forming channel region dopant control in fin field effect transistorIBM·Filed 2014·Granted Jun 28, 2016·2 cites·14 claims
- 4773US2025261452A1Substrate-less silicon controlled rectifier (scr) integrated circuit structuresINTEL CORP·Filed 2025·Application pending·0 cites
- 4872US8217470B2Field effect device including recessed and aligned germanium containing channelCHEN XIANGDONG·Filed 2010·Granted Jul 10, 2012·3 cites·19 claims
- 4972US7790553B2Methods for forming high performance gates and structures thereofIBM·Filed 2008·Granted Sep 7, 2010·5 cites·14 claims
- 5071US11869987B2Gate-all-around integrated circuit structures including varactorsINTEL CORP·Filed 2022·Granted Jan 9, 2024·0 cites·20 claims
Showing the top 50 of 121 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →