Inventor · disambiguated record
James Nolan Hardage
Also filed as: HARDAGE JAMES · HARDAGE JAMES N · HARDAGE JAMES N JR · HARDAGE JAMES NOLAN
28 granted patents·8 pending applications·513 citations·filing 1996–2023
96Inventor score
Top patents by PatentIndex Score
36 records- 0194US6256713B1Bus optimization with read/write coherence including ordering responsive to collisionsIBM·Filed 1999·Granted Jul 3, 2001·100 cites·14 claims
- 0289US11422821B1Age tracking for independent pipelinesAPPLE INC·Filed 2018·Granted Aug 23, 2022·7 cites·20 claims
- 0388US10372500B1Register allocation systemAPPLE INC·Filed 2016·Granted Aug 6, 2019·7 cites·17 claims
- 0488US9958932B2Processor including multiple dissimilar processor cores that implement different portions of instruction set architectureAPPLE INC·Filed 2014·Granted May 1, 2018·10 cites·19 claims
- 0587US6119204AData processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serializationIBM·Filed 1998·Granted Sep 12, 2000·143 cites·16 claims
- 0683US11080188B1Method to ensure forward progress of a processor in the presence of persistent external cache/TLB maintenance requestsAPPLE INC·Filed 2018·Granted Aug 3, 2021·4 cites·20 claims
- 0781US8234489B2Set of system configuration registers having shadow registerWILLIAMSON DAVID JAMES·Filed 2009·Granted Jul 31, 2012·15 cites·18 claims
- 0878US7146468B2Cache memory and method for handling effects of external snoops colliding with in-flight operations internally to the cacheIP FIRST LLC·Filed 2002·Granted Dec 5, 2006·26 cites·34 claims
- 0977US8386754B2Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanismADVANCED RISC MACH LTD·Filed 2009·Granted Feb 26, 2013·9 cites·15 claims
- 1072US9928115B2Hardware migration between dissimilar coresAPPLE INC·Filed 2015·Granted Mar 27, 2018·2 cites·20 claims
- 1164US9081581B2Size mis-match hazard detectionHARDAGE JAMES NOLAN·Filed 2010·Granted Jul 14, 2015·2 cites·19 claims
- 1262US6332179B1Allocation for back-to-back misses in a directory based cacheIBM·Filed 1999·Granted Dec 18, 2001·51 cites·28 claims
- 1357US6636980B1System for launching data on a bus by using first clock for alternately selecting data from two data streams and using second clock for launching data thereafterIBM·Filed 1999·Granted Oct 21, 2003·34 cites·24 claims
- 1456US8250346B2Register renaming of a partially updated data granuleHARDAGE JAMES NOLAN·Filed 2009·Granted Aug 21, 2012·1 cites·16 claims
- 1555US10401945B2Processor including multiple dissimilar processor cores that implement different portions of instruction set architectureAPPLE INC·Filed 2018·Granted Sep 3, 2019·0 cites·19 claims
- 1653US8914615B2Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address formatHARRIS GLEN ANDREW·Filed 2011·Granted Dec 16, 2014·1 cites·23 claims
- 1753US2025094355A1Translation Lookaside Buffer Entry LockingAPPLE INC·Filed 2023·Application pending·0 cites
- 1852US7085885B2Apparatus and method for early cache miss detectionIP FIRST LLC·Filed 2002·Granted Aug 1, 2006·2 cites·35 claims
- 1951US2015082007A1Register mapping with multiple instruction setsADVANCED RISC MACH LTD·Filed 2014·Application pending·0 cites
- 2050US5822764AMethod and circuit for efficiently replacing invalid locked portions of a cache with valid dataMOTOROLA INC·Filed 1996·Granted Oct 13, 1998·23 cites·21 claims
- 2148US2011208950A1Processes, circuits, devices, and systems for scoreboard and other processor improvementsTEXAS INSTRUMENTS INC·Filed 2011·Application pending·0 cites
- 2248US2006095732A1Processes, circuits, devices, and systems for scoreboard and other processor improvementsTRAN THANG M·Filed 2005·Application pending·0 cites
- 2344US6449738B1Apparatus for bus frequency independent wrap I/O testing and method thereforIBM·Filed 1998·Granted Sep 10, 2002·18 cites·12 claims
- 2444US2007260856A1Methods and apparatus to detect data dependencies in an instruction pipelineTRAN THANG M·Filed 2006·Application pending·0 cites
- 2543US6415362B1Method and system for write-through stores of varying sizesIBM·Filed 1999·Granted Jul 2, 2002·16 cites·17 claims
- 2642US5911151AOptimizing block-sized operand movement utilizing standard instructionsMOTOROLA INC·Filed 1996·Granted Jun 8, 1999·15 cites·19 claims
- 2742US2003159003A1Associative cache memory with replacement way information integrated into directoryIP FIRST LLC·Filed 2002·Application pending·0 cites
- 2841US2019220417A1Context Switch OptimizationAPPLE INC·Filed 2018·Application pending·0 cites
- 2940US9058179B2Retirement serialisation of status register access operationsHARDAGE JAMES NOLAN·Filed 2010·Granted Jun 16, 2015·0 cites·18 claims
- 3039US8972701B2Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical registerHARDAGE JAMES NOLAN·Filed 2011·Granted Mar 3, 2015·0 cites·21 claims
- 3139US6269360B1Optimization of ordered stores on a pipelined bus via self-initiated retryIBM·Filed 1998·Granted Jul 31, 2001·10 cites·20 claims
- 3238US2012124346A1Decoding conditional program instructionsHARDAGE JAMES NOLAN·Filed 2010·Application pending·0 cites
- 3337US9946545B2Buffer store with a main store and and auxiliary storeHARDAGE JAMES NOLAN·Filed 2010·Granted Apr 17, 2018·0 cites·15 claims
- 3435US6023737AMulti-stage pipelined data coalescing for improved frequency operationIBM·Filed 1998·Granted Feb 8, 2000·7 cites·20 claims
- 3533US5781916ACache control circuitry and method thereforMOTOROLA INC·Filed 1996·Granted Jul 14, 1998·6 cites·6 claims
- 3632US6408361B1Autonomous way specific tag updateIBM·Filed 1999·Granted Jun 18, 2002·4 cites·16 claims
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