Inventor · disambiguated record
Michael J. Genden
Also filed as: GENDEN MICHAEL J · GENDEN MICHAEL JOSEPH
41 granted patents·4 pending applications·37 citations·filing 2004–2021
96Inventor score
Top patents by PatentIndex Score
45 records- 0193US10387147B2Managing an issue queue for fused instructions and paired instructions in a microprocessorIBM·Filed 2017·Granted Aug 20, 2019·7 cites·11 claims
- 0287US9740620B2Distributed history buffer flush and restore handling in a parallel slice designIBM·Filed 2015·Granted Aug 22, 2017·5 cites·13 claims
- 0386US10394565B2Managing an issue queue for fused instructions and paired instructions in a microprocessorIBM·Filed 2017·Granted Aug 27, 2019·3 cites·6 claims
- 0482US9921833B2Determining of validity of speculative load data after a predetermined period of time in a multi-slice processorIBM·Filed 2015·Granted Mar 20, 2018·3 cites·11 claims
- 0582US9747217B2Distributed history buffer flush and restore handling in a parallel slice designIBM·Filed 2015·Granted Aug 29, 2017·3 cites·7 claims
- 0677US9959123B2Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessorIBM·Filed 2015·Granted May 1, 2018·2 cites·7 claims
- 0773US10747545B2Dual compare of least-significant-bit for dependency wake up from a fused instruction tag in a microprocessorIBM·Filed 2018·Granted Aug 18, 2020·1 cites·20 claims
- 0873US10268482B2Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instructionIBM·Filed 2015·Granted Apr 23, 2019·2 cites·10 claims
- 0971US10740104B2Tagging target branch predictors with context with index modification and late stop fetch on tag mismatchIBM·Filed 2018·Granted Aug 11, 2020·1 cites·17 claims
- 1069US10776122B2Prioritization protocols of conditional branch instructionsIBM·Filed 2018·Granted Sep 15, 2020·1 cites·15 claims
- 1167US10719056B2Merging status and control data in a reservation stationIBM·Filed 2016·Granted Jul 21, 2020·1 cites·20 claims
- 1267US10496412B2Parallel dispatching of multi-operation instructions in a multi-slice computer processorIBM·Filed 2016·Granted Dec 3, 2019·1 cites·14 claims
- 1365US10831501B2Managing an issue queue for fused instructions and paired instructions in a microprocessorIBM·Filed 2019·Granted Nov 10, 2020·0 cites·7 claims
- 1465US10831498B2Managing an issue queue for fused instructions and paired instructions in a microprocessorIBM·Filed 2019·Granted Nov 10, 2020·0 cites·13 claims
- 1565US10175985B2Mechanism for using a reservation station as a scratch registerIBM·Filed 2016·Granted Jan 8, 2019·1 cites·20 claims
- 1665US9971604B2History buffer for multiple-field registersIBM·Filed 2015·Granted May 15, 2018·1 cites·20 claims
- 1764US10108423B2History buffer with single snoop tag for multiple-field registersIBM·Filed 2015·Granted Oct 23, 2018·1 cites·20 claims
- 1864US10067766B2History buffer with hybrid entry support for multiple-field registersIBM·Filed 2015·Granted Sep 4, 2018·1 cites·15 claims
- 1963US10996953B2Low latency execution of floating-point record form instructionsIBM·Filed 2019·Granted May 4, 2021·0 cites·7 claims
- 2063US9996353B2Universal history buffer to support multiple register typesIBM·Filed 2015·Granted Jun 12, 2018·1 cites·20 claims
- 2160US10140127B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2018·Granted Nov 27, 2018·0 cites·13 claims
- 2260US10127047B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2018·Granted Nov 13, 2018·0 cites·7 claims
- 2359US10970079B2Parallel dispatching of multi-operation instructions in a multi-slice computer processorIBM·Filed 2019·Granted Apr 6, 2021·0 cites·14 claims
- 2458US11327766B2Instruction dispatch routingIBM·Filed 2020·Granted May 10, 2022·0 cites·24 claims
- 2558US10678547B2Low latency execution of floating-point record form instructionsIBM·Filed 2017·Granted Jun 9, 2020·0 cites·7 claims
- 2658US10671399B2Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor coreIBM·Filed 2017·Granted Jun 2, 2020·0 cites·8 claims
- 2758US10592246B2Low latency execution of floating-point record form instructionsIBM·Filed 2017·Granted Mar 17, 2020·0 cites·10 claims
- 2857US10671398B2Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor coreIBM·Filed 2017·Granted Jun 2, 2020·0 cites·12 claims
- 2956US9952874B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2016·Granted Apr 24, 2018·0 cites·7 claims
- 3055US9952861B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2015·Granted Apr 24, 2018·0 cites·13 claims
- 3154US9110708B2Region-weighted accounting of multi-threaded processor core according to dispatch stateIBM·Filed 2013·Granted Aug 18, 2015·0 cites·7 claims
- 3252US9928073B2Determining of validity of speculative load data after a predetermined period of time in a multi-slice processorIBM·Filed 2016·Granted Mar 27, 2018·0 cites·6 claims
- 3352US9858078B2Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessorIBM·Filed 2015·Granted Jan 2, 2018·0 cites·13 claims
- 3451US10360036B2Cracked execution of move-to-FPSCR instructionsIBM·Filed 2017·Granted Jul 23, 2019·0 cites·20 claims
- 3551US8230440B2System and method to distribute accumulated processor utilization charges among multiple threadsGENDEN MICHAEL JOSEPH·Filed 2009·Granted Jul 24, 2012·1 cites·17 claims
- 3650US11106466B2Decoupling of conditional branchesIBM·Filed 2018·Granted Aug 31, 2021·0 cites·20 claims
- 3750US7844849B2System and method for identifying and manipulating logic analyzer data from multiple clock domainsIBM·Filed 2007·Granted Nov 30, 2010·1 cites·19 claims
- 3849US9015449B2Region-weighted accounting of multi-threaded processor core according to dispatch stateBISHOP JAMES WILSON·Filed 2011·Granted Apr 21, 2015·0 cites·21 claims
- 3948US10635444B2Shared compare lanes for dependency wake up in a pair-based issue queueIBM·Filed 2018·Granted Apr 28, 2020·0 cites·20 claims
- 4047US12210908B2Routing instructions in a microprocessorIBM·Filed 2021·Granted Jan 28, 2025·0 cites·16 claims
- 4147US10282207B2Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instructionIBM·Filed 2016·Granted May 7, 2019·0 cites·5 claims
- 4245US2006005083A1Performance count tracingIBM·Filed 2004·Application pending·0 cites
- 4344US2020042321A1Low power back-to-back wake up and issue for paired issue queue in a microprocessorIBM·Filed 2018·Application pending·0 cites
- 4439US2017300336A1Fpscr sticky bit handling for out of order instruction executionIBM·Filed 2016·Application pending·0 cites
- 4537US2009058503A1Method to Bridge a Distance Between eFuse Banks That Contain Encoded DataGENDEN MICHAEL JOSEPH·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →