Inventor · disambiguated record
Narendra Sankar
Also filed as: SANKAR NARENDRA
26 granted patents·2 pending applications·1,043 citations·filing 1995–2011
97Inventor score
Files withMIPS TECH INC16NAT SEMICONDUCTOR CORP5CLEARWATER NETWORKS INC3KENDALL CHAD WILLIAM1LINDSAY STEVEN B1
Top patents by PatentIndex Score
28 records- 0194US6789100B2Interstream control and communications for multi-streaming digital processorsMIPS TECH INC·Filed 2002·Granted Sep 7, 2004·80 cites·3 claims
- 0293US7020879B1Interrupt and exception handling for multi-streaming digital processorsMIPS TECH INC·Filed 1999·Granted Mar 28, 2006·143 cites·23 claims
- 0393US6389449B1Interstream control and communications for multi-streaming digital processorsCLEARWATER NETWORKS INC·Filed 1999·Granted May 14, 2002·171 cites·12 claims
- 0492US7467385B2Interrupt and exception handling for multi-streaming digital processorsMIPS TECH INC·Filed 2006·Granted Dec 16, 2008·20 cites·25 claims
- 0592US7032226B1Methods and apparatus for managing a buffer of events in the backgroundMIPS TECH INC·Filed 2000·Granted Apr 18, 2006·69 cites·24 claims
- 0691US6477562B2Prioritized instruction scheduling for multi-streaming processorsCLEARWATER NETWORKS INC·Filed 1998·Granted Nov 5, 2002·184 cites·50 claims
- 0790US7900207B2Interrupt and exception handling for multi-streaming digital processorsMIPS TECH INC·Filed 2008·Granted Mar 1, 2011·15 cites·22 claims
- 0888US7139898B1Fetch and dispatch disassociation apparatus for multistreaming processorsMIPS TECH INC·Filed 2000·Granted Nov 21, 2006·44 cites·16 claims
- 0987US7502876B1Background memory manager that determines if data structures fits in memory with memory state transactions mapMIPS TECH INC·Filed 2000·Granted Mar 10, 2009·49 cites·25 claims
- 1085US7529907B2Method and apparatus for improved computer load and store operationsMIPS TECH INC·Filed 2007·Granted May 5, 2009·12 cites·12 claims
- 1183US6292888B1Register transfer unit for electronic processorCLEARWATER NETWORKS INC·Filed 1999·Granted Sep 18, 2001·112 cites·38 claims
- 1279US7058064B2Queueing system for processors in packet routing operationsMIPS TECH INC·Filed 2000·Granted Jun 6, 2006·23 cites·37 claims
- 1378US7715410B2Queueing system for processors in packet routing operationsMIPS TECH INC·Filed 2006·Granted May 11, 2010·6 cites·21 claims
- 1473US7661112B2Methods and apparatus for managing a buffer of events in the backgroundMIPS TECH INC·Filed 2006·Granted Feb 9, 2010·5 cites·28 claims
- 1573US7551626B2Queueing system for processors in packet routing operationsMIPS TECH INC·Filed 2006·Granted Jun 23, 2009·4 cites·40 claims
- 1672US7926062B2Interrupt and exception handling for multi-streaming digital processorsMIPS TECH INC·Filed 2009·Granted Apr 12, 2011·3 cites·13 claims
- 1772US7406586B2Fetch and dispatch disassociation apparatus for multi-streaming processorsMIPS TECH INC·Filed 2006·Granted Jul 29, 2008·4 cites·20 claims
- 1862US8468540B2Interrupt and exception handling for multi-streaming digital processorsNEMIROVSKY MARIO D·Filed 2011·Granted Jun 18, 2013·1 cites·20 claims
- 1961US7636836B2Fetch and dispatch disassociation apparatus for multistreaming processorsMIPS TECH INC·Filed 2008·Granted Dec 22, 2009·1 cites·16 claims
- 2058US5699506AMethod and apparatus for fault testing a pipelined processorNAT SEMICONDUCTOR CORP·Filed 1995·Granted Dec 16, 1997·33 cites·27 claims
- 2154US7765546B2Interstream control and communications for multi-streaming digital processorsMIPS TECH INC·Filed 2004·Granted Jul 27, 2010·2 cites·21 claims
- 2254US2009187739A1Method and Apparatus for Improved Computer Load and Store OperationsNEMIROVSKY MARIO·Filed 2009·Application pending·0 cites
- 2352US5752273AApparatus and method for efficiently determining addresses for misaligned data stored in memoryNAT SEMICONDUCTOR CORP·Filed 1997·Granted May 12, 1998·27 cites·10 claims
- 2450US5692146AMethod of implementing fast 486TM microprocessor compatible string operationsNAT SEMICONDUCTOR CORP·Filed 1995·Granted Nov 25, 1997·24 cites·8 claims
- 2546US2009110051A1Method and system for reducing the impact of latency on video processingLINDSAY STEVEN B·Filed 2007·Application pending·0 cites
- 2644US8666079B2Decoding and encoding dataKENDALL CHAD WILLIAM·Filed 2008·Granted Mar 4, 2014·0 cites·10 claims
- 2739US5546353APartitioned decode circuit for low power operationNAT SEMICONDUCTOR CORP·Filed 1995·Granted Aug 13, 1996·11 cites·7 claims
- 2830US5815736AArea and time efficient extraction circuitNAT SEMICONDUCTOR CORP·Filed 1995·Granted Sep 29, 1998·0 cites·3 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →